SiGe P-CHANNEL TRI-GATE TRANSISTOR BASED ON BULK SILICON AND FABRICATION METHOD THEREOF

Abstract

A p-channel tri-gate transistor has a silicon fin that protrudes from a bulk silicon substrate, a thin silicon-germanium active layer is formed on three sidewalls of the silicon fin, and a hole well is formed between the gate insulating film and the silicon fin in the active layer surrounded by the tri-gate by a valence band offset electric potential against the silicon fin for moving holes collected in the hole well along the active layer with a high hole-mobility. Thus, it is possible to have the effects of not only an ultra-high speed, low power operation, but also a body biasing through an integral structure of the silicon fin-body. The p-channel tri-gate transistor can be fabricated together with an n-channel FinFET transistor in one substrate by the same CMOS process.

What is claimed is: 
     
         1 . A p-channel tri-gate transistor comprising:
 a silicon fin integrally formed on and protruded from a bulk silicon substrate, the silicon fin providing a body contact to the bulk silicon substrate;   an isolation insulating film filled from the bulk silicon substrate to a predetermined height of the silicon fin;   an active layer having a predetermined thickness formed of Si 1-x Ge x (0.2≦x<1) on both opposite sidewalls and a top surface of the silicon fin on the isolation insulating film;   a gate insulating film formed to surround three sidewalls of the active layer; and   a tri-gate formed on the isolation insulating film to surround the gate insulating film,   wherein a hole well is formed in the active layer between the gate insulating film and the silicon fin by a valence band offset electric potential against the silicon fin and is controlled by the tri-gate.   
     
     
         2 . The p-channel tri-gate transistor of  claim 1 , wherein a germanium Ge fraction x of the active layer is 0.5≦x≦0.9 and the gate insulating film comprises a silicon oxide film. 
     
     
         3 . The p-channel tri-gate transistor of  claim 2 , wherein the gate insulating film further comprises a high-κ film having permittivity higher than that of the silicon oxide film on the silicon oxide film. 
     
     
         4 . The p-channel tri-gate transistor of  claim 1 , wherein the gate insulating film is a high-κ film having permittivity higher than that of a silicon oxide film. 
     
     
         5 . The p-channel tri-gate transistor of  claim 1 ,
 wherein the silicon fin comprises sidewalls that are protruded from the isolation insulating film having a height larger than a width of a top surface and at both ends is integrally formed with source/drain supporters that are protruded from and surrounded by the isolation insulating film having a height of the sidewalls and a width wider than the width of the top surface,   wherein the active layer further comprises source/drain contacts formed on the source/drain supporters with a thickness equal to that on the silicon fin, and   wherein the tri-gate has a width smaller than a height of a surrounding region of the silicon fin and is integrally formed with a gate contact having a width wider than that of the surrounding region.   
     
     
         6 . The p-channel tri-gate transistor of  claim 5 ,
 wherein a plurality of silicon fins having a structure equal to that of the silicon fin are arranged in a row with a predetermined interval between the source and drain supporters,   wherein the active layer is further formed with the same thickness on the plurality of silicon fins that protrude over the isolation insulating film,   wherein the gate insulating film is further formed to surround three sidewalls of each of the active layers formed on the plurality of silicon fins, respectively, and   wherein the tri-gate is formed on the gate insulating films to surround three sidewalls of each of the active layers.   
     
     
         7 . The p-channel tri-gate transistor of  claim 5 , wherein the thickness of the active layer is 1 to 5 nm. 
     
     
         8 . The p-channel tri-gate transistor of  claim 5 ,
 wherein a channel region surrounded by the tri-gate in the active layer is doped with no impurity or n-type impurity having concentration of less than 10 18 /cm 3  and the other regions are doped with p-type impurity having concentration of 10 16  to 10 20 /cm 3 , and   wherein the silicon fin and the source/drain supporters are doped with no impurity or n-type impurity to provide a body contact to the channel region.   
     
     
         9 . A method for fabricating a p-channel tri-gate transistor comprising:
 a first step of depositing an etching stopper thin film on a bulk silicon substrate for a planarization process;   a second step of forming an etching mask on the etching stopper thin film and etching the etching stopper thin film and the bulk silicon substrate for forming an etching stopper pattern, source/drain supporters and a silicon fin;   a third step of depositing an isolation insulating film material on the bulk silicon substrate and polishing by a CMP process until the etching stopper pattern is exposed;   a fourth step of further etching the isolation insulating film material to a predetermined depth and removing the etching stopper pattern for protruding the source/drain supporters and the silicon fin from the isolation insulating film to a predetermined height;   a fifth step of forming a silicon-germanium active layer having a predetermined thickness on the exposed source/drain supporters and the exposed silicon fin;   a sixth step of forming a gate insulating film on the active layer; and   a seventh step of depositing a gate material on the gate insulating film and forming a tri-gate to surround three sidewalls of the silicon fin by patterning and etching.   
     
     
         10 . The method of  claim 9 ,
 wherein the etching mask of the second step is formed by a sidewall spacer patterning process or EUVL (extreme ultraviolet lithography) for forming the silicon fin with a width smaller than that of the source/drain supporter, and   wherein the active layer of the fifth step is directly grown as a silicon-germanium layer having a germanium content on the exposed surfaces of the source/drain supporters and the silicon fin.   
     
     
         11 . The method of  claim 10 , wherein the gate insulating film of the sixth step is a silicon oxide film generated from a surface of the active layer and the active layer has increased germanium content toward the source/drain supporters and the silicon fin in a germanium condensation process of the active layer by a thermal oxidation process. 
     
     
         11 . wherein the gate insulating film further forms a high-κ film having permittivity higher than that of the silicon oxide film on the silicon oxide film after forming the silicon oxide film by the thermal oxidation process. 
     
     
         13 . The method of claim  12 , wherein the thickness of the active layer is 1 to 5 nm. 
     
     
         14 . The method of  claim 10 , wherein the gate insulating film of the sixth step is a high-κ film having permittivity higher than that of a silicon oxide film and formed by a heat treatment based on a plasma process or together a predetermined gas after treating a surface of the active layer. 
     
     
         15 . The method of  claim 10 , wherein the sixth step further proceeds a heat treatment based on a plasma process or together a predetermined gas, after the gate insulating film is formed with a high-κ film having permittivity higher than that of a silicon oxide film, to enhance an interface property between the active layer and the high-κ film. 
     
     
         16 . The method of  claim 9 ,
 wherein the silicon substrate is an intrinsic substrate doped with no impurity or an n-type substrate doped with n-type impurity, and   wherein, after the seventh step, it further comprises steps of removing a gate insulating film by the tri-gate as an etching mask and processing an ion implantation with a p-type impurity.   
     
     
         17 . The method of  claim 16 , wherein the second step forms a plurality of etching masks in a row with a predetermined interval by a fineness pattern and forms a plurality of silicon fins side by side between the source and the drain supporters by etching the bulk silicon substrate through the plurality of etching masks.