Methods for Multi-Wire Routing and Apparatus Implementing Same

Abstract

A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels.

What is claimed is: 
     
         1 . A semiconductor chip, comprising:
 a first conductor including a portion extending in a first direction, the first conductor located within a first level of the semiconductor chip;   a second conductor including a portion extending in the first direction, the second conductor located within the first level of the semiconductor chip;   a third conductor including a portion extending in the first direction, the third conductor located within the first level of the semiconductor chip, the portion of the second conductor positioned between the portions of the first and third conductors in a second direction perpendicular to the first direction; and   a first interlevel conductor contacting the portion of the first conductor and contacting the portion of the fifth conductor.