Non-Volatile Memory With Reduced Program Speed Variation

Abstract

A three-dimensional non-volatile memory is provided with reduced programming variation across word lines. The gate lengths of word lines decrease from the top to the bottom of the memory hole. Increased programming speeds due to a narrow memory hole are offset by a smaller gate length at corresponding positions. A blocking dielectric thickness may also be varied, independently or in combination with a variable word line thickness. The blocking dielectric is formed with a horizontal thickness that is larger at regions adjacent to the lower word line layers and smaller at regions adjacent to the upper word line layers. The larger thickness at the lower word line layers reduces the programming speed in the memory hole for the lower word lines relative to the upper word lines. A variance in programming speed resulting from differences in memory hole diameter may be offset by a corresponding variance in blocking dielectric thickness.

1 . An apparatus, comprising:
 a substrate;   a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over the substrate, the plurality of word line layers including a first word line layer formed below a second word line layer, the first word line layer having a first gate length that is smaller than a second gate length of the second word line layer; and   a first memory hole extending vertically through at least a portion of the stack, the memory hole having a diameter that decreases from an upper region of the stack to a lower region of the stack.   
     
     
         2 . The apparatus of  claim 1 , further comprising:
 a first word line formed in the first word line layer at a first level above a surface of the substrate;   a second word line formed in the second word layer at a second level above the surface of the substrate; and   the first level is a smaller distance from the surface of the substrate than the second level.   
     
     
         3 . The apparatus of  claim 1 , wherein:
 the plurality of word line layers are stacked vertically; and   vertically adjacent word line layers are separated by a corresponding dielectric layer.   
     
     
         4 . The apparatus of  claim 1 , wherein:
 the plurality of word line layers includes a first set of two or more word line layers having the first gate length;   the plurality of word line layers includes a second set of two or more word lines having the second gate length, the second set of two or more word line layers is formed above the first set of two or more word line layers; and   the plurality of word line layers includes a third set of two or more word lines having a third gate length, the third gate length is larger than the second gate length, the third set is formed above the second set.   
     
     
         5 . The apparatus of  claim 1 , wherein:
 each word line layer of the plurality has a gate length that is smaller than the word line layers formed above said each word line layer.   
     
     
         6 . The apparatus of  claim 1 , further comprising:
 the word line layers have gate lengths which are progressively smaller closer to the bottom of the stack.   
     
     
         7 . The apparatus of  claim 1 , further comprising:
 a plurality of memory holes extending through the stack and including the first memory hole, the memory holes have diameters which are progressively smaller closer to a bottom of the stack, the memory holes are columnar and extend at least from a top word line layer of the plurality of word line layers to a bottom word line layer of the plurality of word line layers; and   a plurality of NAND strings arranged along the memory holes, the NAND strings comprise a plurality of memory cells in communication with the plurality of word line layers;   wherein the plurality of memory holes and the plurality of word line layers comprise a non-volatile memory array arranged in a three dimensional structure.   
     
     
         8 . The apparatus of  claim 7 , wherein:
 the first word line layer has a first thickness that defines the first gate length;   the second word line layer has a second thickness that defines the second gate length;   the second thickness is larger than the first thickness; and   each memory cell comprises a control gate formed from a respective word line layer of the plurality of word line layers, a thickness of the respective word line layer defines a gate length of the control gate.   
     
     
         9 . The apparatus of  claim 8 , wherein:
 each NAND string is U-shaped and comprises a source-side column and a drain-side column, each source-side column is arranged along one of the memory holes and each drain-side column is arranged along one of the memory holes.   
     
     
         10 . The apparatus of  claim 8 , wherein:
 each NAND string is straight.   
     
     
         11 . The apparatus of  claim 1 , wherein:
 the first memory hole is filled with a plurality of annular layers comprising a blocking oxide layer, a charge trapping layer, a tunneling layer and a channel layer;   a core region of the first memory hole is filled with a body material, the plurality of annular layers are between the core region and the word line layers in each of the memory holes; and   the diameter of the first memory hole varies based on a diameter of the core region.   
     
     
         12 . The apparatus of  claim 1 , wherein:
 the first word line layer comprises a first control gate of a first memory cell of the plurality of memory cells, the first memory cell is in a first memory hole; and   a thickness of the first word line layer defines the first gate length which corresponds to the first control gate.   
     
     
         13 . The apparatus of  claim 1 , wherein:
 the first memory hole is filled with a blocking oxide layer, a charge trapping layer, a tunnel oxide layer and a channel layer.   
     
     
         14 . A method, comprising:
 forming a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate, the plurality of word line layers including a first word line layer formed below a second word line layer and having a thickness that is less than a thickness of the second word line layer; and   forming a first memory hole extending vertically through at least a portion of the stack, the memory hole having a diameter that decreases from an upper region of the stack to a lower region of the stack.   
     
     
         15 . The method of  claim 14 , wherein forming a plurality of word line layers arranged alternatingly with a plurality of dielectric layers comprises:
 depositing the first word line layer with the first thickness to define a first gate length for a first word line;   depositing a first dielectric layer over the first word line layer;   depositing the second word line layer with the second thickness to define a second gate length of a second word line; and   depositing a second dielectric layer over the second word line layer.   
     
     
         16 . The method of  claim 14 , wherein forming a plurality of word line layers arranged alternatingly with a plurality of dielectric layers comprises:
 depositing a first set of two or more word line layers having the first thickness and depositing a dielectric layer between vertically adjacent word line layers of the first set;   depositing above the first set a second set of two or more word line layers having the second thickness and a dielectric layer between vertically adjacent word line layers of the second set; and   depositing above the second set a third set of two or more word lines having a third thickness and a dielectric layer between vertically adjacent word line layers of the third set, the third thickness is greater than the second thickness.   
     
     
         17 . An apparatus, comprising:
 a substrate;   a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over the substrate, the plurality of word line layers including a first word line formed below a second word line; and   a first memory hole extending vertically through at least a portion of the stack, the memory hole having a diameter that decreases from an upper region of the stack to a lower region of the stack;   a blocking dielectric formed in the first memory hole, the blocking dielectric having a first thickness adjacent to the first word line and a second thickness adjacent to the second word line, the second thickness is less than the first thickness.   
     
     
         18 . The apparatus of  claim 17 , wherein:
 the first memory hole is columnar and extends at least from a top word line layer of the plurality to a bottom word line layer of the plurality;   the blocking dielectric extends from at least the top word line layer to the bottom word line layer; and   the blocking dielectric is tapered with a thickness that is progressively smaller from a region adjacent to the top word line layer to a region adjacent to the bottom word line layer.   
     
     
         19 . The apparatus of  claim 18 , wherein:
 the blocking dielectric thickness varies continuously from the region adjacent to the top word line layer to the region adjacent to the bottom word line layer.   
     
     
         20 . The apparatus of  claim 17 , wherein:
 the first memory hole is columnar and extends at least from a top word line layer of the plurality to a bottom word line layer of the plurality;   the blocking dielectric extends from at least the top word line layer to the bottom word line layer;   the blocking dielectric includes a first region adjacent to a first set of word lines of the plurality, the blocking dielectric having at least the first thickness at the first region, the first set of word lines includes the first word line;   the blocking dielectric includes a second region adjacent to a second set of word lines of the plurality, the blocking dielectric having at least the second thickness at the second region, the second set of word lines includes the second word line and is formed above the first set of word lines; and   the blocking dielectric includes a third region adjacent to a third set of word lines of the plurality, the blocking dielectric having at least the third thickness at the third region, the third thickness is less than the second thickness, the third set of word lines is formed above the second set of word lines.   
     
     
         21 . A method, comprising:
 forming a plurality of word line layers arranged alternatingly with a plurality of dielectric layers in a stack over a substrate, the plurality of word line layers including a first word line formed below a second word line;   forming a first memory hole extending vertically through at least a portion of the stack, the memory hole having a diameter that progressively increases with a distance from a surface of the substrate; and   forming a blocking dielectric in the first memory hole, the blocking dielectric having a first thickness adjacent to the first word line and a second thickness adjacent to the second word line, the second thickness is less than the first thickness.   
     
     
         22 . The method of  claim 19 , wherein forming the blocking dielectric comprises:
 depositing a blocking dielectric layer along at least a portion of a vertical sidewall of the first memory hole; and   etching the blocking dielectric layer to form a tapered profile that is progressively larger from a region adjacent to a top word liner layer to a region adjacent to a bottom word line layer.   
     
     
         23 . The method of  claim 19 , further comprising:
 forming a plurality of sacrificial layers arranged alternatingly with the plurality of dielectric layers in the stack of the substrate prior to forming the plurality of word line layers;   depositing a blocking dielectric layer along at least a first portion of a vertical sidewall of the first memory hole;   forming a trench in the stack adjacent and separated from the memory hole by the plurality of sacrificial layers and the plurality of dielectric layers;   forming a fill layer in the trench and recessing the fill layer to expose a first set of the plurality of sacrificial layers;   etching to remove the first set of sacrificial layers and to decrease a thickness of the blocking dielectric layer at a first region adjacent to the first set of sacrificial layers;   recessing the fill layer to expose a second set of the plurality of sacrificial layers after etching to remove the first set; and   etching to remove the second set of sacrificial layers and to decrease a thickness of the block dielectric layer at the first region and a second region adjacent to the second set of sacrificial layers.   
     
     
         24 . A non-volatile memory apparatus, comprising:
 a plurality of word line layers including a first set of two or more word line layers having a first word line thickness and a second set of two or more word line layers having a second word line thickness, the second set of two or more word line layers is formed above the first set of two or more word line layers, the first word line thickness is smaller than the second word line thickness; and   a first memory hole extending vertically through at least a portion of the plurality of word line layers.   
     
     
         25 . The non-volatile memory apparatus of  claim 24 , further comprising:
 a substrate; and   a plurality of dielectric layers arranged alternatingly with the plurality of word line layers in a stack over the substrate, the first memory hole extends vertically through at least a portion of the stack, the first memory hole has a diameter that decreases from an upper region of the stack to a lower region of the stack.   
     
     
         26 . The non-volatile memory apparatus of  claim 25 , further comprising:
 a plurality of memory holes extending through the stack and including the first memory hole, the plurality of memory holes have diameters which are progressively smaller closer to a bottom of the stack, the memory holes are columnar and extend at least from a top word line layer of the plurality of word line layers to a bottom word line layer of the plurality of word line layers; and   a plurality of NAND strings arranged along the memory holes, the NAND strings comprise a plurality of memory cells in communication with the plurality of word line layers;   wherein the plurality of memory holes and the plurality of word line layers comprise a non-volatile memory array arranged in a three dimensional structure.