Packages with Die Stack Including Exposed Molding Underfill

Abstract

A method includes bonding a first device die onto a top surface of a package substrate, and performing an expose molding on the first device die and the package substrate. At least a lower portion of the first device die is molded in a molding material. A top surface of the molding material is level with or higher than a top surface of the first device die. After the expose molding, a second device die is bonded onto a top surface of the first device die. The second device die is electrically coupled to the first device die through through-silicon vias in a semiconductor substrate of the first device die.

What is claimed is: 
     
         1 . A package comprising:
 a package substrate;   a first device die over and bonded to the package substrate, wherein the first device die comprises:
 a semiconductor substrate; 
 through-silicon vias in the semiconductor substrate; 
 a first plurality of electrical connectors bonded to the package substrate; and 
 a second plurality of electrical connectors, wherein the first and the second plurality of electrical connectors are at opposite sides of the first device die, and wherein respective ones of the first and the second plurality of electrical connectors are interconnected through the through-silicon vias; 
   a molding underfill molding the first device die therein, wherein the molding underfill covers a top surface of the package substrate, and fills a gap between the first device die and the package substrate, and wherein a top surface of the molding underfill is level with or lower than a top surface of the first device die;   a second device die over and bonded to the first device die; and   a metal lid over the second device die, wherein a region interposed between the first device die and the second device die is free of underfill, wherein the metal lid comprises a ring portion attached directly to the first device die using a first thermal interface material (TIM), the ring portion extending completely around a periphery of the second device die, the metal lid being no wider than the first device die.   
     
     
         2 . The package of  claim 1 , wherein the molding underfill has a planar top surface level with a top surface of the first device die. 
     
     
         3 . The package of  claim 1 , wherein the molding underfill has a planar top surface lower than a top surface of the first device die, a lower portion of the first device die being in the molding underfill. 
     
     
         4 . The package of  claim 1  further comprising:
 a second TIM over the second device die, wherein the second device die is attached directly to the metal lid using the second TIM. 
 
     
     
         5 . The package of  claim 1 , wherein the second device die comprises a plurality of dies. 
     
     
         6 . The package of  claim 5 , wherein the plurality of dies comprises a plurality of memory dies. 
     
     
         7 . A package comprising:
 a package substrate;   a first device die bonded onto a top surface of the package substrate, wherein the first device die comprises electrical connectors at a top surface of the first device die;   a molding material extending between the first device die and the package substrate, wherein an upper surface of the molding material is level with the top surface of the first device die;   at least one second device die bonded to the electrical connectors of the first device die, the first device die being interposed between the at least one second device die and the package substrate; and   a lid attached to the first device die with a thermal interface material, the lid having a same width as the first device die, the lid extending over the at least one second device die, the lid comprising a ring portion that extends completely around the at least one second device die in a plan view.   
     
     
         8 . The package of  claim 7 , wherein the package substrate is free of an integrated circuit. 
     
     
         9 . The package of  claim 7 , wherein a lateral width of the molding material is less than a lateral width of the package substrate. 
     
     
         10 . The package of  claim 7 , wherein the lid is attached to a top die of the at least one second device die through an additional thermal interface material. 
     
     
         11 . The package of  claim 7 , wherein the upper surface of the molding material is a substantially flat top surface. 
     
     
         12 . The package of  claim 7 , wherein the first device die is solder bonded to the package substrate. 
     
     
         13 . The package of  claim 7 , wherein the molding material is a single continuous material layer. 
     
     
         14 . A package comprising:
 a first device die bonded to a package substrate;   a molding material interposed between the first device die and the package substrate, the molding material contacting sidewalls of the first device die;   a second device die bonded to the first device die, wherein the second device die is electrically coupled to the first device die through through-semiconductor vias in a semiconductor substrate of the first device die, wherein the molding material has a lateral width less than a lateral width of the package substrate; and   a metal lid over the second device die, wherein the metal lid comprises a ring portion attached directly to the first device die using a first thermal interface material (TIM), the ring portion extending completely around a periphery of second device die, the metal lid having a width less than or equal to a width of the first device die.   
     
     
         15 . The package of  claim 14 , wherein a top surface of the molding material is substantially level with a top surface of the first device die. 
     
     
         16 . The package of  claim 14 , wherein a region interposed between the first device die and the second device die is free of underfill. 
     
     
         17 . The package of  claim 14 , wherein the metal lid is attached directly to the second device die using a second TIM. 
     
     
         18 . The package of  claim 14 , further comprising bonding a third device die onto a top surface of the second device die, where the third device die is electrically coupled to the first device die through additional through-semiconductor vias in an additional semiconductor substrate of the second device die. 
     
     
         19 . The package of  claim 18 , wherein the metal lid is attached directly to the third device die using a second TIM. 
     
     
         20 . The package of  claim 14 , wherein the first device die is solder bonded onto a top surface of the package substrate.