Led having vertical contacts redistributed for flip chip mounting

Abstract

A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface though which light is emitted. A copper layer has a first portion electrically connected to and opposing the bottom surface of the p-type layer. A dielectric wall extends through the copper layer to isolate a second portion of the copper layer from the first portion. A metal shunt electrically connects the second portion of the copper layer to the top surface of the n-type layer. P-metal electrodes electrically connect to the first portion, and n-metal electrodes electrically connect to the second portion, wherein the LED structure forms a flip chip. Other embodiments of the methods and structures are also described.

1 - 6 . (canceled) 
     
     
         7 . A light-emitting device, comprising:
 a first semiconductor structure including a first n-type layer, a first p-type layer, and a first active layer disposed between the first n-type layer and the first p-type layer;   a second semiconductor structure including a second n-type layer, a second p-type layer, and a second active layer disposed between the second n-type layer and the second p-type layer;   a first metal layer including a first portion and a second portion that is electrically insulated from the first portion, the first portion being electrically coupled to the first n-type layer and the second portion being electrically coupled to the second n-type layer; and   a first shunt electrically coupling the first p-type layer to the second portion of the first metal layer;   a second metal layer that is disposed adjacently to the first metal layer; and   a second shunt electrically coupling the second p-type layer to the second metal layer.   
     
     
         8 . The light-emitting device of  claim 7 , wherein the first semiconductor structure and the second semiconductor structure are connected in series by the first shunt. 
     
     
         9 . The light-emitting device of  claim 7 , further comprising a dielectric wall separating the first portion of the first metal layer from the second portion of the first metal layer. 
     
     
         10 . The light emitting device of  claim 7 , further comprising a dielectric wall surrounding the first semiconductor structure and the second semiconductor structure, the dielectric wall being arranged to define a saw line for singulating the light-emitting device. 
     
     
         11 . The light-emitting device of  claim 7 , wherein the first metal layer is formed of copper. 
     
     
         12 . The light-emitting device of  claim 7 , wherein the first metal layer includes a first outer surface, and the second metal layer includes a second outer surface that is substantially flush with the first outer surface. 
     
     
         13 . The light-emitting device of  claim 7 , wherein the first semiconductor structure and the second semiconductor structure are arranged in a flip chip configuration. 
     
     
         14 . A light-emitting device, comprising:
 a first semiconductor structure including a first n-type layer, a first p-type layer, and a first active layer disposed between the first n-type layer and the first p-type layer;   a second semiconductor structure including a second n-type layer, a second p-type layer, and a second active layer disposed between the second n-type layer and the second p-type layer;   a first metal layer including a first portion and a second portion that is electrically insulated from the first portion, the first portion being electrically coupled to the first p-type layer and the second portion being electrically coupled to the second p-type layer; and   a first shunt electrically coupling the first n-type layer to the second portion of the first metal layer;   a second metal layer that is disposed adjacently to the first metal layer; and   a second shunt electrically coupling the second n-type layer to the second metal layer.   
     
     
         15 . The light-emitting device of  claim 14 , wherein the first semiconductor structure and the second semiconductor structure are connected in series by the first shunt. 
     
     
         16 . The light-emitting device of  claim 14 , further comprising a dielectric wall separating the first portion of the first metal layer from the second portion of the first metal layer. 
     
     
         17 . The light emitting device of  claim 14 , further comprising a dielectric wall surrounding the first semiconductor structure and the second semiconductor structure, the dielectric wall being arranged to define a saw line for singulating the light-emitting device. 
     
     
         18 . The light-emitting device of  claim 14 , wherein the first metal layer is formed of copper. 
     
     
         19 . The light-emitting device of  claim 14 , wherein the first metal layer includes a first outer surface, and the second metal layer includes a second outer surface that is substantially flush with the first outer surface. 
     
     
         20 . The light-emitting device of  claim 14 , wherein the first semiconductor structure and the second semiconductor structure are arranged in a flip chip configuration. 
     
     
         21 . A method, comprising:
 forming a first semiconductor structure and a second semiconductor structure, each of the first semiconductor structure and the second semiconductor structure including a respective first conductivity layer, a respective second conductivity layer, and a respective active layer disposed between the respective first conductivity layer and the respective second conductivity layer;   forming a first metal layer including a first portion and a second portion that is electrically insulated from the first portion, the first portion being electrically coupled to the respective first conductivity layer of the first semiconductor structure and the second portion being coupled to the respective first conductivity layer of the second semiconductor structure;   forming a first shunt that is configured to electrically couple the respective second conductivity layer of the first portion to the second portion of the first metal layer;   forming a second metal layer adjacently to the first metal layer; and   forming a second shunt that is configured to electrically couple the second respective conductivity layer of the second semiconductor structure to the second metal layer.   
     
     
         22 . The method of  claim 21 , wherein:
 the respective first conductivity layer of the first semiconductor structure includes a p-type layer;   the respective first conductivity layer of the second semiconductor structure includes a p-type layer;   the respective second conductivity layer of the first semiconductor structure includes an n-type layer; and   the respective second conductivity layer of the second semiconductor structure includes an n-type layer.   
     
     
         23 . The method of  claim 21 , wherein:
 the respective first conductivity layer of the first semiconductor structure includes an n-type layer;   the respective first conductivity layer of the second semiconductor structure includes an n-type layer;   the respective second conductivity layer of the first semiconductor structure includes a p-type layer; and   the respective second conductivity layer of the second semiconductor structure includes a p-type layer.   
     
     
         24 . The method of  claim 21 , wherein the first semiconductor structure and the second semiconductor structure are connected in series by the first shunt. 
     
     
         25 . The method of  claim 21 , further comprising forming a dielectric wall surrounding the first semiconductor structure and the second semiconductor structure. 
     
     
         26 . The method of  claim 21 , wherein the first semiconductor structure and the second semiconductor structure are arranged in a flip chip configuration.