Uv-erasable memory device with uv transmitting window and fabrication method thereof

Abstract

A UV-erasable memory device with a UV transmitting window is disclosed. The UV-erasable memory device includes a substrate, two serially connected PMOS transistors on the substrate; an interlayer dielectric (ILD) layer covering the two PMOS transistors, a first intermetal dielectric (IMD) layer on the ILD layer, an intermediate layer on the first IMD layer, a UV transmitting window in the intermediate layer, and a second intermetal dielectric (IMD) layer on the first IMD layer and in the UV transmitting window.

What is claimed is: 
     
         1 . A method for fabricating a UV-erasable memory device with a UV transmitting window, comprising:
 providing a substrate;   forming two serially connected MOS transistors on said substrate;   covering said two MOS transistors with an interlayer dielectric (ILD) layer;   depositing a first intermetal dielectric (IMD) layer on said ILD layer;   depositing an intermediate layer on said first IMD layer;   forming a UV transmitting window in said intermediate layer; and   depositing a second intermetal dielectric (IMD) layer on said first IMD layer and into said UV transmitting window.   
     
     
         2 . The method for fabricating a UV-erasable memory device with a UV transmitting window according to  claim 1 , wherein said two serially connected MOS transistors comprise a select transistor and a floating gate transistor. 
     
     
         3 . The method for fabricating a UV-erasable memory device with a UV transmitting window according to  claim 2 , wherein said floating gate transistor comprises a polysilicon gate for charge storage. 
     
     
         4 . The method for fabricating a UV-erasable memory device with a UV transmitting window according to  claim 3 , wherein said UV transmitting window is positioned directly above said polysilicon gate for charge storage. 
     
     
         5 . The method for fabricating a UV-erasable memory device with a UV transmitting window according to  claim 1 , wherein said substrate is a P type silicon substrate with an N well. 
     
     
         6 . The method for fabricating a UV-erasable memory device with a UV transmitting window according to  claim 2  further comprising:
 forming a salicide block (SAB) layer covering said polysilicon gate for charge storage. 
 
     
     
         7 . The method for fabricating a UV-erasable memory device with a UV transmitting window according to  claim 6  further comprising:
 depositing a contact etch stop layer on said two serially connected MOS transistors and on said SAB layer. 
 
     
     
         8 . The method for fabricating a UV-erasable memory device with a UV transmitting window according to  claim 7 , wherein said ILD layer is deposited on the contact etch stop layer. 
     
     
         9 . The method for fabricating a UV-erasable memory device with a UV transmitting window according to  claim 1 , wherein said intermediate layer is a silicon oxy-nitride layer. 
     
     
         10 . The method for fabricating a UV-erasable memory device with a UV transmitting window according to  claim 1 , wherein said intermediate layer has a thickness ranging between 1500 angstroms and 2500 angstroms. 
     
     
         11 . A UV-erasable memory device with a UV transmitting window, comprising:
 a substrate;   two serially connected PMOS transistors on said substrate;   an interlayer dielectric (ILD) layer covering said two PMOS transistors;   a first intermetal dielectric (IMD) layer on said ILD layer;   an intermediate layer on said first IMD layer;   a UV transmitting window in said intermediate layer; and   a second intermetal dielectric (IMD) layer on said first IMD layer and in said UV transmitting window.   
     
     
         12 . The UV-erasable memory device with a UV transmitting window according to  claim 11 , wherein said two serially connected PMOS transistors comprise a select transistor and a floating gate transistor. 
     
     
         13 . The UV-erasable memory device with a UV transmitting window according to  claim 12 , wherein said floating gate transistor comprises a polysilicon gate for charge storage. 
     
     
         14 . The UV-erasable memory device with a UV transmitting window according to  claim 13 , wherein said UV transmitting window is positioned directly above said polysilicon gate for charge storage. 
     
     
         15 . The UV-erasable memory device with a UV transmitting window according to  claim 11 , wherein said substrate is a P type silicon substrate with an N well. 
     
     
         16 . The UV-erasable memory device with a UV transmitting window according to  claim 12  further comprising:
 a salicide block (SAB) layer covering said polysilicon gate for charge storage. 
 
     
     
         17 . The UV-erasable memory device with a UV transmitting window according to  claim 16  further comprising:
 a contact etch stop layer on said two serially connected PMOS transistors and on said SAB layer. 
 
     
     
         18 . The UV-erasable memory device with a UV transmitting window according to  claim 17 , wherein said ILD layer is deposited on the contact etch stop layer. 
     
     
         19 . The UV-erasable memory device with a UV transmitting window according to  claim 11 , wherein said intermediate layer is a silicon oxy-nitride layer. 
     
     
         20 . The UV-erasable memory device with a UV transmitting window according to  claim 11 , wherein said intermediate layer has a thickness ranging between 1500 angstroms and 2500 angstroms.