Video processing system using ring buffer and racing-mode ring buffer access control scheme

Abstract

A video processing system has a storage device, an audio/video demultiplexing circuit, and a video decoder. The storage device has a bitstream buffer that is a ring buffer. The audio/video demultiplexing circuit receives an input data, and performs an audio/video demultiplexing operation upon the input data to write data of a video bitstream into the ring buffer. The video decoder fetches data of the video bitstream from the ring buffer, and performs a video decoding operation upon the fetched data of the video bitstream.

What is claimed is: 
     
         1 . A video processing system comprising:
 a storage device, comprising:
 a bitstream buffer, wherein the bitstream buffer is a ring buffer; 
   an audio/video demultiplexing circuit, arranged to receive an input data, and perform an audio/video demultiplexing operation upon the input data to write data of a video bitstream into the ring buffer; and   a video decoder, arranged to fetch data of the video bitstream from the ring buffer, and perform a video decoding operation upon the fetched data of the video bitstream.   
     
     
         2 . The video processing system of  claim 1 , wherein the audio/video demultiplexing circuit is further arranged to update a write pointer to the video decoder, where the write pointer is indicative of a current write address of writing data of the video bitstream into the ring buffer by the audio/video demultiplexing circuit; and the video decoder comprises:
 a read controller, arranged to compare the write pointer with a read pointer, and stop fetching data of the video bitstream from the ring buffer when the read pointer catches up the write pointer, where the read pointer is indicative of a current read address of fetching data of the video bitstream from the ring buffer by the video decoder.   
     
     
         3 . The video processing system of  claim 2 , wherein the read controller does not resume fetching data of the video bitstream from the ring buffer until the audio/video demultiplexing circuit updates the write pointer to a new value. 
     
     
         4 . The video processing system of  claim 1 , wherein the video decoder is further arranged to update a read pointer to the audio/video demultiplexing circuit, where the read pointer is indicative of a current read address of fetching data of the video bitstream from the ring buffer by the video decoder; and the audio/video demultiplexing circuit comprises:
 a write controller, arranged to compare the read pointer with a write pointer, and stop writing data of the video bitstream into the ring buffer when a distance between the write pointer and the read pointer reaches a threshold, where the write pointer is indicative of a current write address of writing data of the video bitstream into the ring buffer by the audio/video demultiplexing circuit.   
     
     
         5 . The video processing system of  claim 4 , wherein the write controller stops writing data of the video bitstream into the ring buffer when the write pointer lags behind the read pointer by the threshold that is equal to a unit increment of the write pointer. 
     
     
         6 . The video processing system of  claim 4 , wherein the write controller does not resume writing data of the video bitstream into the ring buffer until the video decoder updates the read pointer to a new value. 
     
     
         7 . A video processing system comprising:
 a storage device, comprising:
 a display buffer, wherein the display buffer is a ring buffer; 
   a video decoder, arranged to perform a video decoding operation upon data of a video bitstream to write pixel data of a reconstructed video frame into the ring buffer; and   a display engine, arranged to fetch pixel data of the reconstructed video frame from the ring buffer, and drive a display device according to the fetched pixel data of the reconstructed video frame.   
     
     
         8 . The video processing system of  claim 7 , wherein the video decoder comprises a first counter arranged to maintain a first count value indicative of a number of pixel lines that are reconstructed by the video decoder; the display engine comprises a second counter arranged to maintain a second count value indicative of a number of pixel lines that are displayed on the display device through the display engine; and the video processing system further comprises:
 a display control circuit, arranged to receive the first count value from the video decoder, receive the second count value from the display engine, and refer to the first count value and the second first count value to control the display engine.   
     
     
         9 . The video processing system of  claim 8 , wherein the display control circuit is further arranged to compare the first count value with the second count value, and instruct the video decoder to stop writing pixel data of the reconstructed video frame into the ring buffer when a distance between the first count value and the second count value reaches a threshold. 
     
     
         10 . The video processing system of  claim 9 , wherein the display control circuit does not instruct the video decoder to resume writing pixel data of the reconstructed video frame into the ring buffer until the second count value is updated to a new value. 
     
     
         11 . A video processing system comprising:
 a storage device, comprising:
 a data buffer, wherein the data buffer is a ring buffer; 
   a receiving circuit, arranged to receive packets and unpack the packets to write payload data of the packets into the ring buffer; and   an audio/video demultiplexing circuit, arranged to fetch an input data from the ring buffer, and perform an audio/video demultiplexing operation upon the fetched input data, wherein the fetched input data comprise payload data of at least one of the packets.   
     
     
         12 . The video processing system of  claim 11 , wherein the receiving circuit is further arranged to update a write pointer to the audio/video demultiplexing circuit, where the write pointer is indicative of a current write address of writing payload data into the ring buffer by the receiving circuit; and the audio/video demultiplexing circuit comprises:
 a read controller, arranged to compare the write pointer with a read pointer, and stop fetching payload data from the ring buffer when the read pointer catches up the write pointer, where the read pointer is indicative of a current read address of fetching payload data from the ring buffer by the audio/video demultiplexing circuit.   
     
     
         13 . The video processing system of  claim 12 , wherein the read controller does not resume fetching payload data from the ring buffer until the receiving circuit updates the write pointer to a new value. 
     
     
         14 . The video processing system of  claim 11 , wherein the audio/video demultiplexing circuit is further arranged to update a read pointer to the receiving circuit, where the read pointer is indicative of a current read address of fetching payload data from the ring buffer by the audio/video demultiplexing circuit; and the receiving circuit comprises:
 a write controller, arranged to compare the read pointer with a write pointer, and stop writing payload data into the ring buffer when a distance between the write pointer and the read pointer reaches a threshold, where the write pointer is indicative of a current write address of writing payload data into the ring buffer by the receiving circuit.   
     
     
         15 . The video processing system of  claim 14 , wherein the write controller stops writing payload data into the ring buffer when the write pointer lags behind the read pointer by the threshold that is equal to a unit increment of the write pointer. 
     
     
         16 . The video processing system of  claim 14 , wherein the write controller does not resume writing payload data into the ring buffer until the audio/video demultiplexing circuit updates the read pointer to a new value. 
     
     
         17 . The video processing system of  claim 11 , wherein the receiving circuit receives the packets transmitted via a wireless communication link. 
     
     
         18 . The video processing system of  claim 17 , wherein the receiving circuit is a Wireless Fidelity (WiFi) receiver. 
     
     
         19 . The video processing system of  claim 11 , wherein the receiving circuit receives the packets transmitted via a wired communication link. 
     
     
         20 . The video processing system of  claim 19 , wherein the receiving circuit is a Universal Serial Bus (USB) receiver or a High-Definition Multimedia Interface (HDMI) receiver.