Memory device, memory system including the same and operation method of the memory system

Abstract

A memory system includes: a first memory device including a first internal voltage generation circuit; and a second memory device including a second internal voltage generation circuit, wherein the first memory device and the second memory device receive an identical chip enable signal, and when the chip enable signal is disabled, the first internal voltage generation circuit a no the second internal voltage generation circuit are controlled in a standby mode, and when the chip enable signal is enabled, the first internal voltage generation circuit and the second internal voltage generation circuit are independently controlled to have one mode between a weak active mode and a strong active mode.

1 - 10 . (canceled) 
     
     
         11 . A memory device, comprising:
 an internal voltage generation circuit suitable for generating an internal voltage whose drivability is controllable according to a mode of operation of the memory device; and   a mode control circuit suitable for controlling the internal voltage generation circuit in a mode of operation selected among a standby mode, a weak active mode, and a strong active mode based on a chip enable signal and a logical unit number (LUN) address.   
     
     
         12 . The memory device of  claim 11 ,
 wherein the mode control circuit controls the internal voltage generation circuit in a standby mode when the chip enable signal is disabled,   wherein the mode control circuit controls the internal voltage generation circuit in the weak active mode when the chip enable signal is enabled and the LUN address represents non-selection of the memory device, and   wherein the mode control circuit controls the internal voltage generation circuit in the strong active mode when the chip enable signal is enabled and the LUN address represents selection of the memory device.   
     
     
         13 . The memory device of  claim 11 ,
 wherein the internal voltage generation circuit includes a plurality of internal voltage generators for generating the internal voltage,   wherein a first number internal voltage generators are enabled in the standby mode, a second number of internal voltage generators are enabled in the weak active mode, and a third number of internal voltage generators are enabled in the strong active mode, where the third number is greater than the second number and the second number is greater than the first number.   
     
     
         14 . The memory device of  claim 11 , wherein the internal voltage generation circuit includes:
 a standby internal voltage generator suitable for generating the internal voltage of a low drivability in the standby mode;   a weak active internal voltage generator suitable for generating the internal voltage of a middle drivability in the weak active mode; and   a strong active internal voltage generator suitable for generating the internal voltage of a high drivability in the strong active mode.