Configurable Vertical Integration

Abstract

The Configurable Vertical Integration [CVI] invention pertains to methods and apparatus for the enhancement of yields of 3D or stacked integrated circuits and herein referred to as a CVI Integrated Circuit [CVI IC]. The CVI methods require no testing of circuit layer components prior to their fabrication as part of a 3D integrated circuit. The CVI invention uses active circuitry to configure the CVI IC as a means to isolate or prevent the use of defective circuitry. CVI circuit configuration method can be predominately described as a large grain method.

I claim: 
     
         1 . A method of integrated circuit testing of a stacked integrated circuit comprising a plurality of information busing and processing circuit portions, the method comprising:
 one or more circuit portions for enabling and disabling the operation of one or more information processing circuit portions and one or more bus circuit portions;   disabling a plurality of processing circuit portions;   testing at least one enabled processing circuit portion at a time.   
     
     
         2 . A method of information processing using a stacked integrated circuit comprising a plurality of information busing and processing circuit portions, the method comprising:
 one or more circuit portions for enabling and disabling the operation of one or more information processing circuit portions and one or more bus circuit portions;   performing information processing between at least two of the processing circuit portions while at least one of the processing circuit portions is disabled as a result from one of the one or more circuit portions.   
     
     
         3 . A method of information processing using a stacked integrated circuit comprising a plurality of information busing and processing circuit portions, the method comprising:
 one or more circuit portions for enabling and disabling the operation of one or more information processing circuit portions and one or more bus circuit portions;   performing information processing with a plurality of the processing circuit portions and at least one bus circuit portion while at least one of the processing circuit portions or bus circuit portions is disabled by one of the one or more circuit portions for enabling and disabling the operation of circuit portions.