Header encoding and modulation for single carrier physical layer

Abstract

This disclosure describes systems, methods, and devices related to header encoding and modulation. A device may determine an enhanced directional multi-gigabit (EDMG) header field vector comprising one or more bits. The device may determine a first vector associated with a scrambler device, wherein the first vector includes one or more first random bits. The device may scramble the EDMG header field vector based on the first vector. The device may cause to wirelessly transmit to a first device, a codeword associated with the scrambled EDMG header field vector.

What is claimed is: 
     
         1 . A device, the device comprising memory and processing circuitry configured to:
 determine an enhanced directional multi-gigabit (EDMG) header field vector comprising one or more bits;   determine a first vector associated with a scrambler device, wherein the first vector includes one or more first random bits;   cause to modify the EDMG header field vector based on the first vector; and   cause to wirelessly transmit to a first device, a codeword associated with the modified EDMG header field vector.   
     
     
         2 . The device of  claim 1 , wherein the first vector is based at least in part on using a subset of the one or more bits of the EDMG header field vector as initial seed values for the scrambler device. 
     
     
         3 . The device of  claim 2 , wherein the subset of the one or more bits of the EDMG header field vector comprises seven bits. 
     
     
         4 . The device of  claim 1 , wherein the EDMG header field vector is associated with a space-time stream between the device and the first device. 
     
     
         5 . The device of  claim 1 , wherein causing to modify the EDMG header field vector includes performing a bitwise XOR operation between the first vector and the EDMG header field vector. 
     
     
         6 . The device of  claim 1 , wherein the codeword is determined based on performing a bitwise XOR operation between a second vector and an original codeword. 
     
     
         7 . The device of  claim 6 , wherein the original codeword includes a first codeword and a second codeword, wherein the first codeword is comprised of the modified EDMG header field vector and one or more first parity bits, and the second codeword is comprised of the modified EDMG field vector and one or more second parity bits. 
     
     
         8 . The device of  claim 1 , wherein the memory and the processing circuitry are further configured to modulate the codeword associated with the modified EDMG header field vector. 
     
     
         9 . The device of  claim 1 , wherein the memory and the processing circuitry are further configured to:
 determine a first space-time stream between the device and a second device of the one or more devices;   determine a second space-time stream between the device and the second device;   determine a first vector associated with the first space-time stream;   determine a second vector associated with the second space-time stream;   determine a first codeword based on performing a bitwise XOR operation between the first vector and a codeword; and   determine a second scrambled codeword based on performing a bitwise XOR operation between the second vector and the codeword.   
     
     
         10 . The device of  claim 9 , wherein the memory and the processing circuitry are further configured to:
 cause to wirelessly transmit the first codeword to the second device using the first space-time stream; and   cause to wirelessly transmit the second scrambled codeword to the second device using the second space-time stream.   
     
     
         11 . The device of  claim 1 , further comprising a transceiver configured to transmit and receive wireless signals. 
     
     
         12 . The device of  claim 11 , further comprising one or more antennas coupled to the transceiver. 
     
     
         13 . A non-transitory computer-readable medium storing computer-executable instructions which when executed by one or more processors result in performing operations comprising:
 identifying a codeword comprising one or more bits associated with an enhanced directional multi-gigabit (EDMG) header field vector received from a device;   determining a first subset of the one or more bits to be used as initial seed values for a descrambler device;   determining a descrambler vector based at least in part on the first subset of the one or more bits; and   determining an EDMG header field vector based at least in part on the descrambler vector.   
     
     
         14 . The non-transitory computer-readable medium of  claim 13 , wherein the EDMG header field vector comprises 64 bits. 
     
     
         15 . The non-transitory computer-readable medium of  claim 13 , wherein the codeword is modulated using a single carrier modulation. 
     
     
         16 . The non-transitory computer-readable medium of  claim 15 , wherein the single carrier modulation is based on a binary phase shift keying modulation. 
     
     
         17 . The non-transitory computer-readable medium of  claim 13 , wherein a first portion of the descrambler vector is set to one or more zero bits. 
     
     
         18 . A method comprising:
 determining, by one or more processors, an enhanced directional multi-gigabit (EDMG) header field vector comprising one or more bits;   determining a first vector associated with a scrambler device, wherein the first vector includes one or more first random bits;   scrambling the EDMG header field vector based on the first vector; and   causing to wirelessly transmit to a device, a codeword associated with the scrambled EDMG header field vector.   
     
     
         19 . The method of  claim 18 , wherein the first vector is based on using a subset of the one or more bits of the EDMG header field vector as initial seed values for the scrambler device. 
     
     
         20 . The method of  claim 18 , wherein scrambling the EDMG header field vector includes performing a bitwise XOR operation between the first vector and the EDMG header field vector.