Devices and methods of forming sadp on sram and saqp on logic

Abstract

Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.

What is claimed is: 
     
         1 . An intermediate semiconductor device comprising:
 a substrate including a logic area and an SRAM area,   a fin material layer,   a first set of vertical spacers over the logic area; and   a second set of spacers over the SRAM area.   
     
     
         2 . The device of  claim 1 , wherein the first and second sets of spacers comprise an oxide material. 
     
     
         3 . The device of  claim 1 , wherein the first set of spacers comprises a multiple of 4 spacers. 
     
     
         4 . The device of  claim 1 , wherein the second set of spacers comprises a multiple of 2 spacers.