Methods, apparatus and system for providing nmos-only memory cells

Abstract

At least one method, apparatus and system disclosed involves a memory device having a memory cell comprising NMOS only transistors. An SRAM bit cell comprises a first pass gate (PG) NMOS transistor coupled to a first bit line signal and a word line signal; a second PG NMOS transistor coupled to a second bit line signal and the word line signal; a first pull down (PD) NMOS transistor operatively coupled to the first PG NMOS transistor; a second PD NMOS transistor operatively coupled to the second PG NMOS transistor; a first pull up (PU) NMOS transistor operatively coupled to the first PD NMOS transistor; and a second PU NMOS transistor operatively coupled to the second PD NMOS transistor. Each of the back gates of the first and second PU NMOS transistors are coupled to a predetermined voltage signal for biasing the first and second PU NMOS transistors.

1 .- 20 . (canceled) 
     
     
         21 . A method, comprising:
 providing a first pass gate (PG) PMOS transistor coupled to a first bit line signal and a word line signal;   providing a second PG PMOS transistor coupled to a second bit line signal and said word line signal;   providing a first pull down (PD) PMOS transistor operatively coupled to said first PG PMOS transistor;   providing a second PD PMOS transistor operatively coupled to said second PG PMOS transistor;   providing a first pull up (PU) PMOS transistor operatively coupled to said first PD PMOS transistor;   providing a second PU PMOS transistor operatively coupled to said second PD PMOS transistor;   coupling each of the back gates of said first and second PU PMOS transistors to a predetermined voltage signal for biasing said first and second PU PMOS transistors to form a memory cell; and   at least one of (i) coupling a back gate of said first PD transistor to a front gate of said second PD transistor and coupling a back gate of said second PD transistor to a front gate of said first PD transistor, or (ii) coupling a back gate of said first PG transistor to a front gate of said second PD transistor and coupling a back gate of said second PG transistor to a front gate of said first PD transistor.   
     
     
         22 . The method of claim  1 , further comprising coupling said first and second PD PMOS transistors to said first and second PU PMOS transistors to form an inverter to store data. 
     
     
         23 . The method of claim  1 , wherein biasing said first and second PU PMOS transistors comprises biasing said first and second PU PMOS transistors for forming a PMOS resistive load circuit. 
     
     
         24 . The method of claim  1 , wherein biasing said first and second PU PMOS transistors comprises coupling said back gate of said first PU PMOS transistor to a first voltage source and coupling said back gate of said second PU PMOS transistor to a second voltage source. 
     
     
         25 . The method of claim  1 , further comprising biasing said first and second PU PMOS transistors comprises tuning said memory cell to have at least one of a predetermined cell current, a predetermined static noise margin, and a predetermined write margin. 
     
     
         26 . The method of claim  1 , further comprising biasing said first PG PMOS transistor by coupling a back gate of said first PG PMOS transistor to a third voltage source and biasing said second PG PMOS transistor by coupling a back gate of said second PG PMOS transistor to a fourth voltage source. 
     
     
         27 . The method of claim  1 , further comprising:
 coupling said first and second PU transistors to a logic high voltage signal;   coupling said first and second PD transistors to a logic low voltage signal; and   coupling said first and second PG transistors to said logic low voltage signal.   
     
     
         28 . The method of claim  1 , wherein
 coupling a back gate of said first PG transistor to a front gate of said second PD transistor; and   coupling a back gate of said second PG transistor to a front gate of said first PD transistor.   
     
     
         29 . A memory device, comprising:
 an SRAM bit cell comprising:   a first pass gate (PG) PMOS transistor coupled to a first bit line signal and a word line signal;   a second PG PMOS transistor coupled to a second bit line signal and said word line signal;   a first pull down (PD) PMOS transistor operatively coupled to said first PG PMOS transistor;   a second PD PMOS transistor operatively coupled to said second PG PMOS transistor;   a first pull up (PU) PMOS transistor operatively coupled to said first PD PMOS transistor;   a second PU PMOS transistor operatively coupled to said second PD PMOS transistor; and   wherein each of the back gates of said first and second PU PMOS transistors are coupled to a predetermined voltage signal for biasing said first and second PU PMOS transistors, and   wherein a back gate of said first PG transistor is coupled to a front gate of said second PD transistor, and a back gate of said second PG transistor is coupled to a front gate of said first PD transistor.   
     
     
         30 . The memory device of claim  10 , wherein said first and second PD PMOS transistors are coupled with said first and second PU PMOS transistors to form an inverter to store data bit; and wherein said first type is at least one of an PMOS type or a PMOS type. 
     
     
         31 . The memory device of claim  10 , wherein said first and second PU PMOS transistors are configured to be biased for forming a PMOS resistive load circuit. 
     
     
         32 . The memory device of claim  10 , wherein said back gate of said first PU PMOS transistor is coupled to a first voltage source and said back gate of said second PU PMOS transistor is coupled to a second voltage source. 
     
     
         33 . The memory device of claim  10 , wherein said first PG PMOS transistor is configured to be biased by coupling a back gate of said first PG PMOS transistor to a third voltage source, and said second PG PMOS transistor is configured to be biased by coupling a back gate of said second PG PMOS transistor to a fourth voltage source. 
     
     
         34 . The memory device of claim  10 , wherein said SRAM bit cell is configured to be tuned by biasing for providing at least one of a predetermined cell current, a predetermined static noise margin, and a predetermined write margin. 
     
     
         35 . The memory device of claim  10 , wherein said first and second PD PMOS transistors, said first and second PG PMOS transistors, and said first and second PU PMOS transistors are least one of an FD SOI transistor, wherein said FD SOI transistor is at least one of an FD SOI LVT transistor, an FD SOI SLVT transistor, an FD SOI RVT transistor, or an FD SOI HVT transistor. 
     
     
         36 . A system, comprising:
 a semiconductor device processing system to process a semiconductor wafer for manufacturing a memory device, wherein semiconductor device processing system comprising:
 a design unit configured to provide parameters for manufacturing said memory device, wherein said memory device comprising: 
 an SRAM bit cell comprising:
 a first pass gate (PG) PMOS transistor coupled to a first bit line signal and a word line signal; 
 a second PG PMOS transistor coupled to a second bit line signal and said word line signal; 
 a first pull down (PD) PMOS transistor operatively coupled to said first PG PMOS transistor; 
 a second PD PMOS transistor operatively coupled to said second PG PMOS transistor; 
 a first pull up (PU) PMOS transistor operatively coupled to said first PD PMOS transistor; 
 a second PU PMOS transistor operatively coupled to said second PD PMOS transistor; 
 wherein each of the back gates of said first and second PU PMOS transistors are coupled to a predetermined voltage signal for biasing said first and second PU PMOS transistors, and 
 wherein a back gate of said first PG transistor is coupled to a front gate of said second PD transistor, and a back gate of said second PG transistor is coupled to a front gate of said first PD transistor; 
 
 and 
   a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system for manufacturing said memory device.   
     
     
         37 . The system of claim  18 , wherein said SRAM bit cell is configured to be tuned by biasing for providing at least one of a predetermined cell current, a predetermined static noise margin, and a predetermined write margin.