Sort acceleration processors, methods, systems, and instructions

Abstract

A processor of an aspect includes packed data registers, and a decode unit to decode an instruction. The instruction may indicate a first source packed data to include at least four data elements, to indicate a second source packed data to include at least four data elements, and to indicate a destination storage location. An execution unit is coupled with the packed data registers and the decode unit. The execution unit, in response to the instruction, is to store a result packed data in the destination storage location. The result packed data may include at least four indexes that may identify corresponding data element positions in the first and second source packed data. The indexes may be stored in positions in the result packed data that are to represent a sorted order of corresponding data elements in the first and second source packed data.

What is claimed is: 
     
         1 . A processor comprising:
 a plurality of packed data registers;   a decode unit to decode an instruction, the instruction to indicate a first source packed data that is to include a first set of at least four data elements, to indicate a second source packed data that is to include a second set of at least four data elements, and to indicate a destination storage location;   an execution unit coupled with the packed data registers and the decode unit, the execution unit, in response to the instruction, to store a result packed data in the destination storage location,   the result packed data to include at least four indexes,   the indexes to identify corresponding data element positions in the first and second source packed data, and   the indexes to be stored in positions in the result packed data that are to represent a sorted order of corresponding data elements in the first and second source packed data.   
     
     
         2 . The processor of  claim 1 , wherein the execution unit is to store the result packed data in which each of the indexes is to identify a corresponding data element position in each of the first and second source packed data, and wherein the execution unit, in response to the instruction, is to store a result mask that is to have at least four mask elements, in which each mask element is to correspond to a different one of the indexes, and in which each mask element is to indicate whether the data element position for the corresponding index is in the first source packed data or the second source packed data. 
     
     
         3 . The processor of  claim 2 , further comprising a mask register to store the result mask, and wherein the instruction is included in an instruction set that includes a second instruction that is able to indicate the result mask as a predicate operand to predicate a packed data operation. 
     
     
         4 . The processor of  claim 1 , wherein the execution unit is to store the result packed data in which each of the indexes is to identify the corresponding single data element in one of the first and second source packed data. 
     
     
         5 . The processor of  claim 1 , wherein the execution unit, in response to the instruction, is to store a second result packed data in a second destination storage location that is to be indicated by the instruction, the second result packed data to include the data elements from the first and second source packed data that correspond to the indexes stored in positions of the second result packed data that reflect the sorted order. 
     
     
         6 . The processor of  claim 1 , wherein the decode unit is to decode the instruction that is to indicate the first source packed data having the at least four data elements that are assumed to be in sorted order for the instruction, and that is to indicate the second source packed data having the at least four data elements that are assumed to be in sorted order for the instruction. 
     
     
         7 . The processor of  claim 1 , wherein the decode unit is to decode the instruction that is to indicate the first source packed data having the at least four data elements that are not assumed to be in sorted order for the instruction, and that is to indicate the second source packed data having the at least four data elements that are not assumed to be in sorted order for the instruction. 
     
     
         8 . The processor of  claim 1 , wherein the execution unit is to store the result packed data in which the indexes are to be stored in the positions that are to represent the sorted order of the corresponding data elements that are to include a smallest half of all of the data elements of the first and second source packed data. 
     
     
         9 . The processor of  claim 1 , wherein the execution unit is to store the result packed data in which the indexes are to be stored in the positions that are to represent the sorted order of the corresponding data elements that are to include a largest half of all of the data elements of the first and second source packed data. 
     
     
         10 . The processor of  claim 1 , wherein the decode unit is to decode the instruction that is to indicate the first source packed data that is to include at least eight data elements which are each to have one of 32-bits and 64-bits. 
     
     
         11 . A method in a processor comprising:
 receiving an instruction, the instruction indicating a first source packed data including a first set of at least four data elements, indicating a second source packed data including a second set of at least four data elements, and indicating a destination storage location; and   storing result packed data in the destination storage location in response to the instruction, the result packed data including,   at least four indexes,   the indexes identifying corresponding data element positions in the first and second source packed data, and   the indexes stored in positions in the result packed data that represent a sorted order of corresponding data elements in the first and second source packed data.   
     
     
         12 . The method of  claim 11 , wherein receiving comprises receiving the instruction indicating the first source packed data having the at least four data elements in sorted order. 
     
     
         13 . The method of  claim 11 , wherein storing the result packed data comprises storing result packed data in which each of the indexes identifies the corresponding single data element in one of the first and second source packed data. 
     
     
         14 . A processor comprising:
 a plurality of packed data registers;   a decode unit to decode an instruction, the instruction to indicate a source packed data that is to include at least four data elements that are not in a sorted order, and to indicate a destination storage location;   an execution unit coupled with the packed data registers and the decode unit, the execution unit, in response to the instruction, to store a result packed data in the destination storage location,   the result packed data to include at least four indexes,   the indexes to identify corresponding data elements in the source packed data, and   the indexes to be stored in positions in the result packed data that are to represent the sorted order of the corresponding data elements in the source packed data.   
     
     
         15 . The processor of  claim 14 , wherein the execution unit, in response to the instruction, is to store a second result packed data in a second destination storage location that is to be indicated by the instruction, the second result packed data to include the corresponding data elements stored in positions of the second result packed data that reflect the sorted order. 
     
     
         16 . The processor of  claim 14 , wherein the result packed data is to include indexes corresponding to all data elements in the source packed data. 
     
     
         17 . The processor of  claim 14 , wherein the decode unit is to decode the instruction that is to indicate the source packed data that is to include at least eight data elements that are each to have one of 32-bits and 64-bits. 
     
     
         18 . The processor of  claim 14 , wherein the packed data registers are able to store 512-bit packed data.