Package structure and manufacturing method thereof

Abstract

A package structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a chip, a circuit layer structure, and an insulating protective layer. The composite layer of the non-conductor inorganic material and the organic material is disposed on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the sealant, and the chip has electrode pads. The circuit layer structure is formed on the sealant and the chip. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protective layer has openings, so as to expose parts of the surface of the circuit layer structure in the openings.

What is claimed is: 
     
         1 . A package structure, comprising:
 a metal layer;   a composite layer of a non-conductor inorganic material and an organic material disposed on the metal layer;   a sealant bonded on the composite layer of the non-conductive inorganic material and the organic material;   a chip embedded in the sealant, wherein the chip has a plurality of electrode pads, and the electrode pads are exposed from the sealant;   a circuit layer structure formed on the sealant and the chip, wherein the circuit layer structure comprises at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the circuit layer is located on the dielectric layer and extends into the conductive blind holes, and a bottommost circuit layer is electrically connected to the electrode pads through the conductive blind holes; and   an insulating protective layer formed on the circuit layer structure, wherein the insulating protective layer has a plurality of openings, so as to expose parts of a surface of the circuit layer structure in the openings.   
     
     
         2 . The package structure of  claim 1 , wherein the chip has a chip bottom surface exposed from the sealant. 
     
     
         3 . The package structure of  claim 1 , wherein a material of the composite layer of the non-conductor inorganic material and the organic material comprises a composite material composed of a ceramic material and a polymer material. 
     
     
         4 . The package structure of  claim 3 , wherein the ceramic material comprises zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof, and the polymer material comprises epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof. 
     
     
         5 . The package structure of  claim 1 , wherein the composite layer of the non-conductor inorganic material and the organic material is an imitation nacreous layer. 
     
     
         6 . A method of manufacturing package structures, comprising:
 providing a carrier, wherein the carrier comprises a supporting layer having opposite two surfaces, a release layer disposed on each of the two surfaces, and a metal layer disposed on each of the release layers;   disposing a composite layer of a non-conductor inorganic material and an organic material on each of the metal layers;   bonding a chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material, wherein the chip embedded substrate comprises a plurality of chips and a sealant, the chips are embedded in the sealant, each of the chips has a plurality of electrode pads, and the electrode pads are exposed from the sealant;   forming a circuit layer structure on each of the chip embedded substrates, wherein the circuit layer structure comprises at least one dielectric layer and at least one circuit layer, the dielectric layer has a plurality of conductive blind holes, the circuit layer is located on the dielectric layer and extends into the conductive blind holes, and a bottommost circuit layer is electrically connected to the electrode pads through the conductive blind holes;   forming an insulating protective layer on each of the circuit layer structures, wherein the insulating protective layer has a plurality of openings, so as to expose parts of a surface of the circuit layer structure in the openings;   removing the supporting layer and the release layers to form two package substrates; and   cutting each of the package substrates to obtain a plurality of the package structures.   
     
     
         7 . The method of  claim 6 , wherein each of the sealants has a sealant bottom surface, and each of the chips has a chip bottom surface, wherein the step of bonding the chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material comprises:
 grinding the sealant bottom surface to expose the chip bottom surface, so as to form a ground chip embedded substrate; and   bonding the ground chip embedded substrate on each of the composite layers of the non-conductor inorganic material and the organic material.   
     
     
         8 . The method of  claim 6 , wherein a material of each of the composite layers of the non-conductor inorganic material and the organic material comprises a composite material composed of a ceramic material and a polymer material. 
     
     
         9 . The method of  claim 8 , wherein the ceramic material comprises zirconia, aluminum oxide, silicon nitride, silicon carbide, silicon oxide, or a combination thereof, and the polymer material comprises epoxy resins, polyimide, liquid crystal polymers, methacrylate resins, vinyl phenyl resins, allyl resins, polyacrylate resins, polyether resins, polyolefin resins, polyamide resins, polysiloxane resins, or a combination thereof. 
     
     
         10 . The method of  claim 6 , wherein each of the composite layers of the non-conductor inorganic material and the organic material is an imitation nacreous layer.