US2017367180A1PendingUtilityA1

Array type discrete decoupling under bga grid

Assignee: ALCATEL-LUCENT CANADA INCPriority: Jun 16, 2016Filed: Jun 16, 2016Published: Dec 21, 2017
Est. expiryJun 16, 2036(~9.9 yrs left)· nominal 20-yr term from priority
H05K 1/0296H05K 3/0005H05K 1/181H05K 1/111H05K 2201/10734H05K 1/113H05K 2201/10719H05K 1/114Y02P70/50H05K 2201/10712H05K 2201/10704
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Claims

Abstract

Various exemplary embodiments relate to a printed circuit board (PCB) for electrically connecting a discrete array component including a pattern formed on the PCB which is a merger of a set of via pads and a discrete array component; wherein the pattern is generated by a pin mapping between the discrete array component and a via grid array on the PCB; and wherein the pattern is formed of a metal etched during a manufacturing process of the PCB.

Claims

exact text as granted — not AI-modified
1 . A printed circuit board (PCB) for electrically connecting a discrete array component comprising:
 a pattern formed on the PCB including a plurality of merged pads, wherein the merged pads are via pads and discrete array component pads;   wherein each merged pad is determined by a pin mapping between the discrete array component and a via grid array on the PCB that associates a discrete array pad with a via pad:   wherein each merged pad is based upon a shape of the associated via pad and the discrete array component pad; and   wherein the pattern is formed of a metal etched during a manufacturing process of the PCB.   
     
     
         2 . The PCB of  claim 1 , wherein the PCB includes a plurality of the patterns formed on the PCB. 
     
     
         3 . The PCB of  claim 1 , wherein the discrete array component includes a plurality of pins. 
     
     
         4 . The PCB of  claim 1 , wherein the PCB includes a plurality of different patterns etched on the PCB. 
     
     
         5 . The PCB of  claim 1 , wherein the metal is copper. 
     
     
         6 . The PCB of  claim 1 , wherein the pattern is generated by having verified that a pin mapping between the discrete array component and a ball grid array on an opposite side of the PCB is feasible. 
     
     
         7 . A computer aided design (CAD) tool implemented on a computing device for soldering a discrete array component on a printed circuit board (PCB) for use with mounting a component comprising:
 a design tool mode configured to identify a placement of the discrete array component on the PCB and to verify whether pin mapping between the discrete array component and a ball grid array (BGA) on the opposite side of the PCB is feasible;   a design tool mode configured to determine the geometry of a set of via pads to be associated with the discrete array component and a geometry for the discrete array component; and   a design tool mode configured to generate a pattern on the PCB associated with a merger of the via pads and discrete array component.   
     
     
         8 . The CAD tool of  claim 7 , wherein the discrete component is made up a plurality of components. 
     
     
         9 . The CAD tool of  claim 8 , wherein the plurality of components include resistors, capacitors, diodes, transistors, and other small form factor discrete devices. 
     
     
         10 . The CAD tool of  claim 7 , wherein the discrete component is made up of a plurality of pins. 
     
     
         11 . The CAD tool of  claim 7 , wherein the discrete component may be any size or geometry. 
     
     
         12 . The CAD tool of  claim 7 , wherein the pattern is analyzed to determine the portions of the generated pattern to be masked by solder mask. 
     
     
         13 . The PCB of  claim 1 , wherein the spacing between the discrete pads is different than the spacing between the via pads. 
     
     
         14 . A printed circuit board (PCB) for electrically connecting a discrete array component comprising:
 a pattern formed on the PCB which is a merger of a set of via pads and a discrete array component, the discrete array component having at least a  2  X  2  grid;   wherein the pattern is generated by a pin mapping between the discrete array component and a via grid array on the PCB,   wherein the pattern is formed of a metal etched during a manufacturing process of the PCB.   
     
     
         15 . The PCB of  claim 14 , wherein the spacing between the discrete pads is different than the spacing between the via pads.

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