Semiconductor device and method of manufacturing the semiconductor device

Abstract

A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nMOS gate electrode formed in an nMOS region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.

What what is claimed is: 
     
         1 . A method of manufacturing a semiconductor device comprising:
 forming a first amorphous silicon film on a semiconductor substrate;   implanting an impurity including at least one of P, Ge, and Si to the first amorphous silicon film in a nMOS region of the semiconductor substrate;   forming a second amorphous silicon film on top of the first amorphous silicon film;   forming a gate electrode pattern in each of the first and second amorphous silicon films; and   polycrystalizing the first amorphous silicon film in the nMOS region by performing a thermal process after the forming of the gate electrode pattern.   
     
     
         2 . The method of manufacturing a semiconductor device as claimed in  claim 1 , further comprising:
 implanting an impurity including at least one of B, BF2, Ge, N, and F to the first amorphous silicon film in a pMOS region of the semiconductor substrate.   
     
     
         3 . The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein the thermal process includes performing an activation annealing process after forming a source and a drain by implanting an impurity into the nMOS region and the pMOS region of the semiconductor substrate. 
     
     
         4 . The method of manufacturing a semiconductor device as claimed in  claim 1 , further comprising:
 performing an activation annealing process after forming a source and a drain by implanting an impurity into the nMOS region and the pMOS region of the semiconductor substrate;   wherein the thermal process and the activation annealing process are performed separately.   
     
     
         5 . The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein the thermal process is performed by using the heat generated when performing selective epitaxial growth. 
     
     
         6 . The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein the thermal process is performed by using the heat generated when forming sidewall spacers at the sides of the gate electrode patterns of the first and second amorphous films. 
     
     
         7 . The method of manufacturing a semiconductor device as claimed in  claim 1 , further comprising:
 forming a source and a drain in the pMOS region of the semiconductor substrate after the forming of the gate electrode pattern;   wherein the thermal process is performed by using the heat generated when forming an SiGe layer by performing selective epitaxial growth.   
     
     
         8 . The method of manufacturing a semiconductor device as claimed in  claim 6 , wherein the forming of the sidewall spacers includes
 forming a first insulation film covering the gate electrode pattern, and   forming a second insulation film on top of the first insulation film,   wherein the thermal process is performed by using the heat generated when performing the forming of the second insulation film.   
     
     
         9 . The method of manufacturing a semiconductor device as claimed in  claim 8 , wherein the first insulation film is formed at a temperature that does not cause crystallization of amorphous silicon, wherein the second insulation film is formed at a temperature that causes crystallization of the amorphous silicon.