System and method for manufacturing a cavity down fabricated carrier

Abstract

A method of fabricating a receptacle down BGA carrier having a top surface and a bottom surface, the method comprising combining a conductive portion and a molded dielectric portion, said dielectric portion having an inner surface intersecting said top surface, said inner surface forming a cavity for receiving a die; selectively etching part of said conductive portion; and applying solder resist to a portion of a top surface of said conductive portion.

We claim: 
     
         1 . A method of fabricating a receptacle down BGA carrier having a top surface and a bottom surface, the method comprising:
 combining a conductive portion and a molded dielectric portion, the dielectric portion having an inner surface intersecting the top surface, the inner surface forming a cavity for receiving a die;   selectively etching part of the conductive portion; and   applying solder resist to a portion of a top surface of the conductive portion.   
     
     
         2 . The method of  claim 1 , wherein the dielectric portion is molded from a polymerized molding compound. 
     
     
         3 . The method of  claim 2 , wherein the polymerized molding compound comprises a binding material. 
     
     
         4 . The method of  claim 2 , wherein the binding material comprises an epoxy filled with inorganic fillers. 
     
     
         5 . The method of  claim 4 , wherein the inorganic fillers comprise one of either at least one of silicon dioxide or silicon carbide, or a plastic compound. 
     
     
         6 . The method of  claim 1 , wherein the inner surface orthogonally intersects the top surface. 
     
     
         7 . The method of  claim 1 , wherein the inner surface non-orthogonally intersects the top surface. 
     
     
         8 . The method of  claim 1 , wherein the shape of the cavity is one of ether a square, a rectangle, a triangle, a circle or an irregular shape. 
     
     
         9 . The method of  claim 1 , further comprising selectively plating the conductive portion at said top surface. 
     
     
         10 . The method of  claim 9 , wherein the selective plating is shaped to form bonding fingers and BGA pads. 
     
     
         11 . The method of  claim 9 , wherein the selective plating comprises applying a photo-imageable plating resist to the top surface, exposing the photo-imageable plating resist to an image pattern, developing the resist, depositing metal on unexposed portions of the plating resist, and stripping the plating resist. 
     
     
         12 . The method of  claim 11 , wherein the metal is one of either Ag, Ni/Au or Pd. 
     
     
         13 . The method of  claim 9 , wherein selectively etching comprises applying a photo-imageable etching resist to the top surface, exposing the photo-imageable etching resist to an image pattern, developing the resist, and stripping the etching resist. 
     
     
         14 . The method of  claim 1 , wherein applying solder resist to the top surface is performed selectively in accordance with a predetermined shape. 
     
     
         15 . The method of  claim 14 , wherein the predetermined shape is such that areas of the conductive portion forming BGA pads and bonding fingers are left exposed at the top surface. 
     
     
         16 . The method of  claim 15 , further including applying an adhesive layer to exposed portions of the bottom surface. 
     
     
         17 . The method of  claim 16 , wherein the adhesive layer comprises one of either a thermoset epoxy or film. 
     
     
         18 . The method of  claim 16 , further including applying a heat spreader to the bottom surface of the adhesive layer. 
     
     
         19 . A receptacle down BGA carrier fabricated according to the method of  claim 1 .