Memory system and method of controlling nonvolatile memory

Abstract

According to one embodiment, a memory controller of a memory system includes a command issuing unit, a decoder, a counter, and a statistical processor. The command issuing unit issues a first command for single read of first data from a nonvolatile memory. The decoder performs first error correction on the read first data. The counter counts a number of times of multiple reads. The statistical processor performs statistical processing of results of the multiple reads, and outputs second data obtained by the statistical processing. When the decoder is unable to perform the first error correction on the read first data, the command issuing unit issues a second command for multiple reads of the first data.

What is claimed is: 
     
         1 . A memory system comprising:
 a nonvolatile memory configured to store data; and   a controller circuit configured to control the nonvolatile memory,   the controller circuit instructing the nonvolatile memory to search a first read voltage to read data from the nonvolatile memory, by reading data from the nonvolatile memory with N different read voltages, N being a natural number larger than three, and   the controller circuit instructing the nonvolatile memory to search a second read voltage to read data from the nonvolatile memory, by reading data from the nonvolatile memory with M different read voltages, M being a natural number larger than N.   
     
     
         2 . The memory system according to  claim 1 , wherein
 the controller circuit includes a decoder configured to perform an error correction on data read from the nonvolatile memory, and   when the controller circuit attempts to read first data stored in the nonvolatile memory, the controller circuit instructs the nonvolatile memory to search the second read voltage if the decoder detects an uncorrectable error in second data with a first error correction code, the second data being the first data read from the nonvolatile memory by using the first read voltage.   
     
     
         3 . The memory system according to  claim 2 , wherein
 the decoder performs an error correction on third data with a second error correction code, the third data being the first data read from the nonvolatile memory by using the second read voltage.   
     
     
         4 . The memory system according to  claim 3 , wherein
 the error correction capability with the second error correction code is equal to or higher than the error correction capability with the first error correction code.   
     
     
         5 . The memory system according to  claim 1 , wherein
 a difference between two adjacent read voltages used in searching the second read voltage is smaller than a difference between two adjacent read voltages used in searching the first read voltage.   
     
     
         6 . The memory system according to  claim 1 , wherein
 the controller circuit instructs the nonvolatile memory to search the first read voltage by issuing one command.   
     
     
         7 . The memory system according to  claim 1 , wherein
 the controller circuit instructs the nonvolatile memory to search the first read voltage by issuing N read commands.   
     
     
         8 . A memory system comprising:
 a nonvolatile memory configured to store data; and   a controller circuit configured to control the nonvolatile memory and including a decoder configured to perform an error correction on data read from the nonvolatile memory, wherein,   when the controller circuit attempts to read first data stored in the nonvolatile memory, if the decoder detects an uncorrectable error in second data with a first error correction code, the second data being the first data read from the nonvolatile memory by using a first read voltage, the controller circuit instructs the nonvolatile memory to search a second read voltage, by reading data from the nonvolatile memory with N different read voltages, N being a natural number larger than three.   
     
     
         9 . The memory system according to  claim 8 , wherein
 the decoder performs an error correction on third data with a second error correction code, the third data being the first data read from the nonvolatile memory by using the second read voltage.   
     
     
         10 . The memory system according to  claim 9 , wherein
 the error correction capability with the second error correction code is equal to or higher than the error correction capability with the first error correction code.   
     
     
         11 . The memory system according to  claim 8 , wherein
 the controller circuit instructs the nonvolatile memory to search the second read voltage by issuing one command.   
     
     
         12 . The memory system according to  claim 8 , wherein
 the controller circuit instructs the nonvolatile memory to search the second read voltage by issuing N read commands.   
     
     
         13 . A method of controlling a memory system, the memory system including a nonvolatile memory configured to store data, the method comprising:
 searching a first read voltage to read data from the nonvolatile memory by reading data from the nonvolatile memory with N different read voltages, N being a natural number larger than three, and   searching a second read voltage to read data from the nonvolatile memory by reading data from the nonvolatile memory with M different read voltages, M being a natural number larger than N.   
     
     
         14 . The method according to  claim 13 , further comprising:
 in attempting to read first data stored in the nonvolatile memory, performing an error correction on second data with a first error correction code, the second data being the first data read from the nonvolatile memory by using the first read voltage; and   searching the second read voltage when an uncorrectable error is detected in the second data.   
     
     
         15 . The method according to  claim 14 , further comprising
 performing an error correction on third data with a second error correction code, the third data being the first data read from the nonvolatile memory by using the second read voltage.   
     
     
         16 . The method according to  claim 15 , wherein
 the error correction capability with the second error correction code is equal to or higher than the error correction capability with the first error correction code.   
     
     
         17 . The method according to  claim 13 , wherein
 a difference between two adjacent read voltages in searching the second read voltage is smaller than a difference between two adjacent read voltages in searching the first read voltage.   
     
     
         18 . The method according to  claim 13 , the memory system further including a controller circuit configured to control the nonvolatile memory, wherein
 the first read voltage is searched by issuing one command from the controller circuit to the nonvolatile memory.   
     
     
         19 . The method according to  claim 13 , the memory system further including a controller circuit configured to control the nonvolatile memory, wherein
 the first read voltage is searched by issuing N read commands from the controller circuit to the nonvolatile memory.