Enhancing Cache Performance by Utilizing Scrubbed State Indicators Associated With Cache Entries

Abstract

Systems and methods for improving write-back cache performance by utilizing scrubbed state indicators associated with the cache entries. The example system may comprise: a cache comprising a plurality of cache entries; a processing core, coupled to the cache; and a cache controller configured to maintain a plurality of indicators corresponding to a plurality of cache entries, wherein each indicator of the plurality of indicators indicates whether a corresponding cache entry has been scrubbed by synchronizing the cache entry with a next level memory after the cache entry has been modified.

What is claimed is: 
     
         1 . A system, comprising:
 a cache comprising a plurality of cache entries;   a processing core, coupled to the cache; and   a cache controller configured to maintain a plurality of indicators corresponding to a plurality of cache entries, wherein each indicator of the plurality of indicators indicates whether a corresponding cache entry has been scrubbed by synchronizing the cache entry with a next level memory after the cache entry has been modified.   
     
     
         2 . The system of  claim 1 , wherein the cache is provided by a set-associated cache comprising a plurality of sets, each set comprising a plurality of cache entries. 
     
     
         3 . The system of  claim 1 , wherein each indicator is provided by a single bit. 
     
     
         4 . The system of  claim 1 , wherein each indicator is provided by a counter indicating a number of times the corresponding cache entry has been synchronized with the next level memory after having been modified. 
     
     
         5 . The system of  claim 1 , wherein the cache controller is configured to utilize the plurality of indicators corresponding to the plurality of cache entries for implementing a certain cache scrubbing policy. 
     
     
         6 . The system of  claim 1 , wherein the cache controller is configured to designate a number of cache ways to be maintained in a clean state. 
     
     
         7 . The system of  claim 1 , wherein the cache controller is configured to designate a number of least recently cache entries to be maintained in a clean state. 
     
     
         8 . The system of  claim 1 , wherein the cache controller is configured to designate a number of least recently cache entries to be maintained in a clean state in each set of the cache. 
     
     
         9 . The system of  claim 1 , wherein the cache controller is configured to designate a power-saving goal and a performance-enabling goal, wherein the power-saving goal specifies a first number of cache entries to be maintained in a clean state, and wherein the performance-enabling goal specifies a second number of cache entries to be maintained in a clean state. 
     
     
         10 . The system of  claim 9 , wherein the power-saving goal designates for scrubbing a cache entry comprised by a cache set responsive to determining that a number of clean entries within the set falls below a specified threshold. 
     
     
         11 . The system of  claim 9 , wherein the performance-enabling goal designates for scrubbing at least a threshold number of entries of a pre-defined number of least-recently used entries. 
     
     
         12 . The system of  claim 1 , wherein the cache controller is configured to utilize the plurality of indicators corresponding to a plurality of cache entries to exclude from scrubbing one or more cache entries that have previously been scrubbed. 
     
     
         13 . The system of  claim 1 , wherein the system is provided by a system-on-chip (SoC). 
     
     
         14 . A method, comprising:
 selecting, by a cache controller, a plurality of cache entries to be scrubbed in accordance with a cache scrubbing policy;   using a plurality of scrubbed state indicators associated with the plurality of cache entries to identify, among the plurality cache entries, one or more cache entries that has previously been scrubbed; and   scrubbing the plurality of cache entries except for at least one identified previously scrubbed cache entry.   
     
     
         15 . The method of  claim 14 , further comprising:
 updating scrubbed state indicators associated with scrubbed cache entries.   
     
     
         16 . The method of  claim 14 , wherein each indicator is provided by a single bit. 
     
     
         17 . The method of  claim 14 , wherein each indicator is provided by a counter indicating a number of times the corresponding cache entry has been synchronized with the next level memory after having been modified. 
     
     
         18 . An integrated circuit comprising a cache controller, the cache controller configured to:
 maintain a plurality of indicators corresponding to a plurality of cache entries, wherein each indicator of the plurality of indicators indicates whether a corresponding cache entry has been scrubbed by synchronizing the cache entry with a next level memory after the cache entry has been modified.   
     
     
         19 . The integrated circuit of  claim 18 , wherein each indicator is provided by a single bit. 
     
     
         20 . The integrated circuit of  claim 18 , wherein each indicator is provided by a counter indicating a number of times the corresponding cache entry has been synchronized with the next level memory after having been modified.