Instruction and logic to provide vector scatter-op and gather-op functionality

Abstract

Instructions and logic provide vector scatter-op and/or gather-op functionality. In some embodiments, responsive to an instruction specifying: a gather and a second operation, a destination register, an operand register, and a memory address; execution units read values in a mask register, wherein fields in the mask register correspond to offset indices in the indices register for data elements in memory. A first mask value indicates the element has not been gathered from memory and a second value indicates that the element does not need to be, or has already been gathered. For each having the first value, the data element is gathered from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. When all mask register fields have the second value, the second operation is performed using corresponding data in the destination and operand registers to generate results.

What is claimed is: 
     
         1 . A processor comprising:
 a decoder to decode a single-instruction multiple-data (SIMD) instruction, the SIMD instruction to indicate a first source register that is to have a first plurality of data elements, to indicate a second source register that is to have a second plurality of data elements that are each to correspond to a different data element of the first plurality of data elements, to indicate a third source register that is to have a plurality of indices that are each to correspond to a different data element of the first plurality of data elements; and   one or more execution units, coupled with the decoder, and responsive to the decoded SIMD instruction, to:   perform a operation on each of data elements of the first plurality of data elements, and a corresponding data element of the second plurality of data elements, to generate a corresponding result data element; and   store each result data element to a location in memory that is to be identified by a corresponding index of the plurality of indices.   
     
     
         2 . The processor of  claim 1 , wherein the operation is binary. 
     
     
         3 . The processor of  claim 2 , wherein the operation is addition. 
     
     
         4 . The processor of  claim 2 , wherein the operation is multiplication. 
     
     
         5 . The processor of  claim 1 , wherein the operation is ternary 
     
     
         6 . The processor of  claim 1 , wherein the first source register comprises 512-bits, and wherein the data elements of the first source register are one of 32-bit data elements and 64-bit data elements. 
     
     
         7 . A processor comprising:
 a decoder to decode a single-instruction multiple-data (SIMD) instruction, the SIMD instruction to indicate a first source register that is to have a first plurality of data elements, to indicate a second source register that is to have a second plurality of data elements that are each to correspond to a different data element of the first plurality of data elements, to indicate a third source register that is to have a plurality of indices that are each to correspond to a different data element of the first plurality of data elements, and to indicate a mask register that is to have a plurality of mask fields that are each to correspond to a different data element of the first plurality of data elements; and   one or more execution units, coupled with the decoder, and responsive to the decoded SIMD instruction, to:   perform a binary operation, which is one of addition and multiplication, on each of the data elements of the first plurality of data elements, which corresponds to a mask field that is to have a first value, and a corresponding data element of the second plurality of data elements, to generate corresponding result data elements; and   store each of the result data elements to a location in memory that is to be identified by a corresponding index of the plurality of indices.   
     
     
         8 . The processor of  claim 7 , wherein the operation is multiplication. 
     
     
         9 . The processor of  claim 7 , wherein the operation is addition. 
     
     
         10 . The processor of  claim 7 , wherein each mask field is a single bit, and wherein each first value is binary one. 
     
     
         11 . The processor of  claim 7 , wherein the one or more execution units, responsive to the decoded SIMD instruction, are to perform the operation on each of the data elements of the first plurality of data elements that is to correspond to the mask field that is to have the first value before storing any of the result data elements to memory. 
     
     
         12 . The processor of  claim 7 , wherein the one or more execution units, responsive to the decoded SIMD instruction, are also to change a value of the corresponding mask field from the first value to a second value, for each of the result data elements that are to be stored to the memory, wherein each mask field with the first value is to indicate that corresponding result data element has not yet been, but needs to be, stored to memory. 
     
     
         13 . A processor comprising:
 a decoder to decode a single-instruction multiple-data (SIMD) instruction, the SIMD instruction to indicate a first source register that is to have a first plurality of data elements, to indicate a second source register that is to have a second plurality of data elements that are each to correspond to a different data element of the first plurality of data elements, to indicate a third source register that is to have a plurality of indices that are each to correspond to a different data element of the first plurality of data elements, and to indicate a mask register that is to have a plurality of mask fields that are each to correspond to a different data element of the first plurality of data elements; and   one or more execution units, coupled with the decoder, and responsive to the decoded SIMD instruction, to:   perform an operation, which is one of a binary operation and a ternary operation, on each of the data elements of the first plurality of data elements, which corresponds to a mask field that is to have a first value, and a corresponding data element of the second plurality of data elements, to generate corresponding result data elements; and   store each of the result data elements to a location in memory that is to be identified by a corresponding index of the plurality of indices.   
     
     
         14 . The processor of  claim 13 , wherein the one or more execution units, responsive to the decoded SIMD instruction, are to perform the operation on each of the data elements of the first plurality of data elements that is to correspond to the mask field that is to have the first value before storing any of the result data elements to memory. 
     
     
         15 . The processor of  claim 13 , wherein the one or more execution units, responsive to the decoded SIMD instruction, are also to change a value of the corresponding mask field from the first value to a second value, for each of the result data elements that are to be stored to the memory, wherein each mask field with the first value is to indicate that corresponding result data element has not yet been, but needs to be, stored to memory. 
     
     
         16 . The processor of  claim 13 , wherein the operation is binary and is multiplication. 
     
     
         17 . The processor of  claim 13 , wherein the operation is binary and is addition. 
     
     
         18 . The processor of  claim 13 , wherein the operation is ternary. 
     
     
         19 . A processor comprising:
 a decoder to decode a single-instruction multiple-data (SIMD) instruction, the SIMD instruction to indicate a first source register that is to have a first plurality of data elements, to indicate a second source register that is to have a second plurality of data elements that are each to correspond to a different data element of the first plurality of data elements, to indicate a third source register that is to have a plurality of indices that are each to correspond to a different data element of the first plurality of data elements, and to indicate a mask register that is to have a plurality of mask bits that are each to correspond to a different data element of the first plurality of data elements; and   one or more execution units, coupled with the decoder, and responsive to the decoded SIMD instruction, to:   perform a binary operation, which is one of addition and multiplication, on each of the data elements of the first plurality of data elements, which corresponds to a mask bit that is to have a first value of one, and a corresponding data element of the second plurality of data elements, to generate corresponding result data elements;   store each of the result data elements to a location in memory that is to be identified by a corresponding index of the plurality of indices; and   change a value of the corresponding mask bit from the first value of one to a value of zero, for each of the result data elements that are to be stored to the memory, wherein each mask bit with the first value of one is to indicate that a corresponding result data element has not yet been, but needs to be, stored to memory.   
     
     
         20 . The processor of  claim 19 , wherein the one or more execution units, responsive to the decoded SIMD instruction, are to perform the operation on each of the data elements of the first plurality of data elements that is to correspond to the mask field that is to have the first value before storing any of the result data elements to memory.