Remote memory access using memory mapped addressing among multiple compute nodes

Abstract

An example method for facilitating remote memory access with memory mapped addressing among multiple compute nodes is executed at an input/output (IO) adapter in communication with the compute nodes over a Peripheral Component Interconnect Express (PCIE) bus, the method including: receiving a memory request from a first compute node to permit access by a second compute node to a local memory region of the first compute node; generating a remap window region in a memory element of the IO adapter, the remap window region corresponding to a base address register (BAR) of the second compute node; and configuring the remap window region to point to the local memory region of the first compute node, wherein access by the second compute node to the BAR corresponding with the remap window region results in direct access of the local memory region of the first compute node by the second compute node.

What is claimed is: 
     
         1 . A method executed at an input/output (IO) adapter in communication with a plurality of compute nodes over a Peripheral Component Interconnect Express (PCIE) bus, the method comprising:
 receiving a memory request from a first compute node to permit access by a second compute node to a local memory region of the first compute node;   generating a remap window region in a memory element of the IO adapter, the remap window region corresponding to a base address register (BAR) of the second compute node in the IO adapter; and   configuring the remap window region to point to the local memory region of the first compute node, wherein access by the second compute node to the BAR corresponding with the remap window region results in direct access of the local memory region of the first compute node by the second compute node.   
     
     
         2 . The method of  claim 1 , wherein the compute nodes are associated with unique PCIE endpoints on the PCIE bus. 
     
     
         3 . The method of  claim 1 , wherein the direct access of the local memory region of the first compute node by the second compute node does not involve operating systems of the first compute node and the second compute node. 
     
     
         4 . The method of  claim 1 , wherein the BAR of the second compute node comprises one of a plurality of BARs associated with the second compute node. 
     
     
         5 . The method of  claim 4 . wherein a device driver of the second compute node associates the BAR with the remap window region, such that an application executing in the second compute node can access the local memory region of the first compute node through appropriate access requests to the BAR using the device driver. 
     
     
         6 . The method of  claim 1 , wherein configuring the remap window region comprises configuring a remap window base in a BAR Resource Table (BRT) to be a start address of the local memory region. 
     
     
         7 . The method of  claim 1 , wherein the memory request comprises a host identifier of the second compute node and address of the local memory region of the first compute node. 
     
     
         8 . The method of  claim 7 , wherein the host identifier is obtained from a resource map providing identifying information of the compute nodes in communication with the IO adapter over the PCIE bus. 
     
     
         9 . The method of  claim 1 , wherein the compute nodes comprise microservers executing in a single chassis. 
     
     
         10 . The method of  claim 1 , wherein the compute nodes comprise virtual machines executing in a single hypervisor. 
     
     
         11 . Non-transitory tangible media that includes instructions for execution, which when executed by a processor of a IO adapter in communication with a plurality of compute nodes over a PCIE bus, is operable to perform operations comprising:
 receiving a memory request from a first compute node to permit access by a second compute node to a local memory region of the first compute node;   generating a remap window region in a memory element of the IO adapter, the remap window region corresponding to a BAR of the second compute node in the IO adapter; and   configuring the remap window region to point to the local memory region of the first compute node, wherein access by the second compute node to the BAR corresponding with the remap window region results in direct access of the local memory region of the first compute node by the second compute node.   
     
     
         12 . The media of  claim 11 , wherein the BAR of the second compute node comprises one of a plurality of BARs associated with the second compute node. 
     
     
         13 . The media of  claim 11 , wherein a device driver of the second compute node associates the BAR with the remap window region, such that an application executing in the second compute node can access the local memory region of the first compute node through appropriate access requests to the BAR using the device driver. 
     
     
         14 . The media of  claim 11 , wherein configuring the remap window region comprises configuring a remap window base in a BRT to be a start address of the local memory region. 
     
     
         15 . The media of  claim 11 , wherein the compute nodes comprise microservers executing in a single chassis. 
     
     
         16 . An apparatus, comprising:
 an IO adapter;   a plurality of compute nodes in communication with the IO adapter over a PCIE bus;   a physical memory for storing data; and   a processor, wherein the processor executes instructions associated with the data, wherein the processor and the physical memory cooperate, such that the apparatus is configured for:
 receiving a memory request from a first compute node to permit access by a second compute node to a local memory region of the first compute node; 
 generating a remap window region in a memory element of the IO adapter, the remap window region corresponding to a BAR of the second compute node in the IO adapter; and 
 configuring the remap window region to point to the local memory region of the first compute node, wherein access by the second compute node to the BAR corresponding with the remap window region results in direct access of the local memory region of the first compute node by the second compute node. 
   
     
     
         17 . The apparatus of  claim 16 , wherein the BAR of the second compute node comprises one of a plurality of BARs associated with the second compute node. 
     
     
         18 . The apparatus of  claim 16 , wherein a device driver of the second compute node associates the BAR with the remap window region, such that an application executing in the second compute node can access the local memory region of the first compute node through appropriate access requests to the BAR using the device driver. 
     
     
         19 . The apparatus of  claim 16 , wherein configuring the remap window region comprises configuring a remap window base in a BRT to be a start address of the local memory region. 
     
     
         20 . The apparatus of  claim 16 , wherein the compute nodes comprise microservers executing in a single chassis.