Test mode circuit with serialized i/o and semiconductor memory device including the same

Abstract

A semiconductor system may include a controller and a semiconductor device. The controller may output command/address signals. The semiconductor device may generate a plurality of control codes from the command/address signals in a test mode according to a combination of the command/address signals. The semiconductor device may output a first output datum generated by serializing the plurality of control codes, and the first output datum, through a single pad.

What is claimed is: 
     
         1 . A semiconductor system comprising:
 a controller suitable for outputting command/address signals; and   a semiconductor device suitable for generating a plurality of control codes from the command/address signals, while in a test mode, according to a combination of the command/address signals and suitable for outputting a first output datum generated by serializing the plurality of control codes through a single pad.   
     
     
         2 . The semiconductor system of  claim 1 , wherein the first output datum is generated by sequentially serializing the plurality of control codes while the semiconductor device is in the test mode. 
     
     
         3 . The semiconductor system of  claim 1 , wherein the semiconductor device outputs a plurality of output data generated from the plurality of control codes through a plurality of pads if the semiconductor device is in a normal operation. 
     
     
         4 . The semiconductor system of  claim 1 ,
 wherein if the combination of the command/address signals is a first combination, the semiconductor device generates the plurality of control codes from the command/address signals; and   wherein if the combination of the command/address signals is a second combination, the semiconductor device serializes the plurality of control codes to output the serialized control codes as the first output datum.