System for selecting a task to be executed according to an output from a task control circuit

Abstract

The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory into a processing register and execute a task in accordance with the data in the processing register. The save circuit is provided with a plurality of save registers respectively associated with a plurality of tasks. In executing a predetermined system call, the execution control circuit notifies the task control circuit as such. The task control circuit switches between tasks for execution upon receipt of the system call signal, by saving, in the save register associated with a task being executed, the data in the processing register, selecting a task to be executed next, and loading data in the save register associated with the selected task into the processing register.

1 . A task control circuit coupled through signal lines to a processor which executes a task, comprising:
 a plurality of state storage units, each of the state storage units being provided for a corresponding one of a plurality of tasks and storing state data of the corresponding one of the tasks;   a task selecting circuit selecting a task for execution according to the state data in the state storage units; and   a task switching circuit updating the state data in the state storage units when a system call signal is received from the processor,   wherein each of the state storage units comprises a timeout counter for storing a timeout value, the timeout counter periodically decrementing a timeout value associated with the task in a WAIT state,   wherein the task selecting circuit includes a timeout detecting circuit detecting that the timeout value associated with the task in the WAIT state is decremented to a predetermined value to output a task ID of a detected task in the WAIT state to the task switching circuit, and   wherein the task switching circuit updates the state data in a state storage unit associated with the detected task from the WAIT state to a READY state.   
     
     
         2 . The task control circuit according to  claim 1 , wherein the timeout value is set when the processor sends the system call signal. 
     
     
         3 . The task control circuit according to  claim 1 ,
 wherein the timeout value is set in a processing register included in the processor, and   wherein the task switching circuit reads the timeout value from the processing register.   
     
     
         4 . The task control circuit according to  claim 1 , wherein the timeout counter updates the timeout value temporally in parallel with execution of the task by the processor. 
     
     
         5 . The task control circuit according to  claim 1 , wherein the task switching circuit switches between tasks for execution by:
 selecting a task to be executed next from an output from the task selecting circuit when the system call signal is received;   saving data stored in a processing register included in the processor into a predetermined storage area and updating the state data in the state storage unit associated with a task being executed from a RUN state to another state; and   loading data for the selected task saved in the predetermined storage area into the processing register and changing the state data in the state storage unit associated with the selected task to the RUN state.   
     
     
         6 . The task control circuit according to  claim 1 , wherein the task switching circuit halts operation of the processor when the task ID is input from the timeout detecting circuit. 
     
     
         7 . A task control device coupled through signal lines to a processor, the task control device, comprising:
 state registers each storing state data representing an execution state of a task;   a task switching circuit controlling the execution states of the tasks; and   a timeout counter,   wherein when the processor executes a system call instruction bounded by a timeout condition,   the task switching circuit sets state data of a task that has executed the system call instruction bounded by the timeout condition to a WAIT state and starts updating the timeout counter, and   the task switching circuit updates state data of a timed-out task from the WAIT state to a READY state.