Semiconductor Devices and Methods for Forming the Same

Abstract

A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a cell array area and a step area;   a cell gate conductive pattern in the cell array area and extending to the step area;   a cell vertical structure in the cell array area and extending through the cell gate conductive pattern;   a cell gate contact structure on the cell gate conductive pattern in the step area; and   a cell gate contact region in the cell gate conductive pattern in the step area and aligned with the cell gate contact structure,   wherein the cell gate conductive pattern and the cell gate contact region comprise doped silicon,   wherein the cell gate contact region that is in the step area comprises implanted impurities of a first element, and   wherein a concentration of the implanted impurities of the first element in the cell gate contact region is higher than a concentration of implanted impurities of the first element in the cell gate conductive pattern in the cell array area.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising an insulating layer on the cell gate conductive pattern,
 wherein the insulating layer has a contact hole on the cell gate conductive pattern in the step area,   wherein the cell gate contact structure is in the contact hole, and   wherein a width of the cell gate contact region is substantially equal to a width of the contact hole.   
     
     
         3 . The semiconductor device of  claim 1 , wherein the cell gate conductive pattern does not substantially comprise the implanted impurities of the first element in the cell array area. 
     
     
         4 . The semiconductor device of  claim 1 , further comprising:
 a cell body contact region including the first element as a dopant; and   a cell body contact structure on the cell body contact region,   wherein the first element comprises a first conductivity type, and   wherein the cell body contact region comprises the first conductivity type.   
     
     
         5 . The semiconductor device of  claim 1 , further comprising:
 a semiconductor substrate including a cell active region, a first peripheral active region, and a second peripheral active region;   a first peripheral contact region in the first peripheral active region of the semiconductor substrate; and   a second peripheral contact region in the second peripheral active region of the semiconductor substrate,   wherein the cell array area and the step area are in the cell active region of the semiconductor substrate.   
     
     
         6 . The semiconductor device of  claim 5 ,
 wherein the first peripheral contact region comprises a first conductivity type including the first element as a dopant, and   wherein the second peripheral contact region comprises a second conductivity type including a second element as a dopant, wherein the second element is of a group different from the first element.   
     
     
         7 . The semiconductor device of  claim 5 , further comprising:
 a first cell band active region on the cell active region;   a second cell band active region on the first cell band active region;   a cell body contact structure in the first cell band active region; and   a cell body contact region in the first cell band active region including the first element as a dopant,   wherein the first element comprises a first conductivity type, and   wherein the cell body contact region comprises the first conductivity type.   
     
     
         8 . The semiconductor device of  claim 1 , further comprising:
 a first peripheral transistor;   a second peripheral transistor;   a first peripheral contact structure spaced apart from the cell gate conductive pattern;   a second peripheral contact structure spaced apart from the first peripheral contact structure;   a first peripheral contact region under the first peripheral contact structure; and   a second peripheral contact region under the second peripheral contact structure,   wherein the first peripheral transistor comprises a first peripheral gate and a first peripheral impurity region of a first conductivity type,   wherein the second peripheral transistor comprises a second peripheral gate and a second peripheral impurity region of a second conductivity type different from the first conductivity type,   wherein the first peripheral contact region is in the first peripheral impurity region and comprises an impurity concentration higher than the first peripheral impurity region,   wherein the second peripheral contact region is in the second peripheral impurity region and comprises an impurity concentration higher than the second peripheral impurity region,   wherein the first peripheral contact region comprises the first conductivity type including the first element as a dopant, and   wherein the second peripheral contact region comprises the second conductivity type including a second element as a dopant, wherein the second element is of a group different from the first element.   
     
     
         9 . The semiconductor device of  claim 8 , wherein the cell gate contact structure comprises an upper surface that is co-planar with an upper surface of the first peripheral contact structure and a lower surface that is not co-planar with a lower surface of the first peripheral contact structure. 
     
     
         10 . The semiconductor device of  claim 8 , wherein a lower surface of the cell gate contact structure is not co-planar with a lower surface of the first peripheral contact structure. 
     
     
         11 . A semiconductor device, comprising:
 a cell semiconductor layer;   a plurality of cell gate conductive patterns on the cell semiconductor layer and extending from a cell array area to a step area, wherein the plurality of cell gate conductive patterns comprise doped semiconductor;   a cell vertical structure extending through the plurality of cell gate conductive patterns; and   a plurality of cell gate contact structures on respective ones of the plurality of cell gate conductive patterns in the step area,   wherein each of the plurality of cell gate conductive patterns comprises a cell gate contact region under a respective one of the plurality of cell gate contact structures,   wherein the cell gate contact region that is in the step area comprises implanted impurities of a first element, and   wherein a concentration of the implanted impurities of the first element in the cell gate contact region is higher than a concentration of implanted impurities of the first element in the respective one of the plurality of cell gate conductive patterns in the cell array area.   
     
     
         12 . The semiconductor device of  claim 11 , wherein the doped semiconductor comprises doped silicon. 
     
     
         13 . The semiconductor device of  claim 11 , further comprising an insulating layer on the plurality of cell gate conductive patterns,
 wherein the insulating layer has contact holes on each of the plurality of cell gate conductive patterns in the step area, and the plurality of cell gate contact structures are in the contact holes.   
     
     
         14 . The semiconductor device of  claim 13 , wherein a width of the cell gate contact region in the step area is substantially equal to a width of a respective one of the contact holes. 
     
     
         15 . The semiconductor device of  claim 13 , wherein the cell vertical structure comprises a data storage layer and a channel semiconductor pattern. 
     
     
         16 . The semiconductor device of  claim 13 , wherein the plurality of cell gate conductive patterns do not substantially comprise implanted impurities of the first element in the cell array area. 
     
     
         17 . A semiconductor device, comprising:
 a vertical memory cell structure extending from a cell semiconductor layer in a first direction perpendicular to a surface of the cell semiconductor layer;   a cell gate conductive pattern on a portion of the vertical memory cell structure, wherein the cell gate conductive pattern comprises doped silicon; and   a cell gate contact structure extending in the first direction from a cell gate contact region in a portion of the cell gate conductive pattern,   wherein the cell gate contact region comprises implanted impurities of a first element, and   a concentration of the implanted impurities of the first element in the cell gate contact region is higher than a concentration of the first element in another portion of the cell gate conductive pattern other than the cell gate contact region.   
     
     
         18 . The semiconductor device of  claim 17 , further comprising an insulating layer on the cell gate conductive pattern,
 wherein the insulating layer has contact hole on the cell gate conductive pattern,   wherein the cell gate contact structure is in the contact hole, and   wherein a width of the cell gate contact region is substantially equal to a width of the contact hole.   
     
     
         19 . The semiconductor device of  claim 17 , wherein the another portion of the cell gate conductive pattern does not substantially comprise implanted impurities of the first element. 
     
     
         20 . The semiconductor device of  claim 17 , further comprising:
 a cell body contact structure extending in the first direction from a cell body contact region in the cell semiconductor layer; and   a peripheral contact structure extending in the first direction from a peripheral contact region and electrically connected to a peripheral transistor,   wherein the first element comprises a first conductivity type, and   wherein one or more of the cell body contact region and the peripheral contact region comprises a semiconductor doped with the first element and comprises the first conductivity type.