Laser scribe structures for a wafer

Abstract

Structures that include an identification marking and fabrication methods for such structures. A chip is formed within a usable area of a wafer, and a marking region is formed on the wafer. The marking region is comprised of a conductor used to form a last metal layer of an interconnect structure for the chip. The identification marking is formed in the conductor of the marking region. After the identification marking is formed, a dielectric layer is deposited on the marking region. The dielectric layer on the marking region is planarized.

What is claimed is: 
     
         1 . A structure comprising:
 a wafer including a usable area, a wiring region, and a chip within the usable area;   a marking region on the wafer;   an identification marking in the marking region; and   a dielectric layer on the marking region and the wiring region, the dielectric layer having a planarized top surface.   
     
     
         2 . The structure of  claim 1  wherein the marking region is comprised of a metal. 
     
     
         3 . The structure of  claim 2  wherein the wiring region is comprised of the metal. 
     
     
         4 . The structure of  claim 3  wherein the wiring region is a topmost metal layer. 
     
     
         5 . The structure of  claim 1  wherein the marking region is comprised of a metal, and the identification marking includes a plurality of elements that are laser scribed into the metal. 
     
     
         6 . The structure of  claim 1  wherein the identification marking includes a raised portion and a recessed portion that are covered by the dielectric layer. 
     
     
         7 . The structure of  claim 6  further comprising:
 a substrate adhesively bonded to the planarized top surface of the dielectric layer. 
 
     
     
         8 . The structure of  claim 1  further comprising:
 a substrate adhesively bonded to the planarized top surface of the dielectric layer. 
 
     
     
         9 . The structure of  claim 8  wherein the identification marking is located radially inward from an outer peripheral edge of the wafer. 
     
     
         10 . The structure of  claim 1  wherein the marking region is outside of the usable area. 
     
     
         11 . The structure of  claim 1  wherein a portion of the wafer underlying the marking region is free of device structures. 
     
     
         12 . The structure of  claim 1  wherein the marking region is not used for making electrical connections, and the marking region is not a component of the chip.