Method for embedding silicon die into a stacked package

Abstract

Several embodiments of microelectronic configurations with logic components and associated methods of manufacturing are disclosed herein. In one embodiment, the configuration includes a substrate with a recess, a first die carried by the substrate wherein the die substantially covers the recess, and a logic component carried by the die in a location exposed by the recess. The logic component can be substantially coplanar with the substrate. The die is electrically connected to a terminal on a one side of the substrate, and the logic component is electrically connected to a terminal on an opposite side of the substrate.

We claim: 
     
         1 . A method for assembling a microelectronic device package, comprising:
 forming an interposer substrate with a recess;   attaching a die structure to a one side of the interposer substrate;   attaching a logic component to the microelectronic device package such that at least a portion of the logic component is positioned between the one side of the interposer substrate and a opposite side of the interposer substrate, and such that at least a portion of the logic component is accessible through the recess on the opposite side; and   electrically connecting the die structure and the logic component to bond pads on the interposer substrate.   
     
     
         2 . The method of  claim 1  wherein forming an interposer substrate comprises forming the recess to extend from the one side of the interposer substrate to the opposite side of the interposer substrate, the method further comprising:
 attaching the logic component to the die structure on a portion of the die structure exposed by the recess. 
 
     
     
         3 . The method of  claim 1  wherein forming an interposer substrate with a recess comprises forming a blind hole in the opposite side of the interposer substrate, the method further comprising:
 attaching the logic component to the interposer substrate at a base of the blind hole. 
 
     
     
         4 . The method of  claim 1  wherein the die structure comprises a plurality of dies stacked together and electrically connected by a plurality of through-silicon-vias. 
     
     
         5 . The method of  claim 1  wherein the die structure comprises a plurality of dies with a spacer between each of the dies. 
     
     
         6 . A microelectronic device, comprising:
 a substrate having a first side and a second side, a recess open at the first side and extending partially, but not completely, through the substrate, the recess having a base, recess sidewalls, and a plurality of terminals at the second side;   one or more first dies attached to the second side of the substrate, the one or more first dies having integrated circuitry and bond sites electrically connected to the plurality of terminals; and   a second die having a major surface and die sidewalls, the second die being in the recess at the first side of the substrate and attached to the base of the recess, the second die being electrically connected to the plurality of terminals,   wherein the base has a first width between the recess sidewalls, the major surface has a second width between the logic component sidewalls, and the first width is substantially the same as the second width.   
     
     
         7 . The microelectronic device of  claim 6 , wherein the one or more first dies form a die structure comprising a plurality of first dies attached to the first side of the substrate. 
     
     
         8 . The microelectronic device of  claim 6 , wherein the recess is centrally located on the substrate. 
     
     
         9 . The microelectronic device of  claim 6 , wherein the first dies are electrically connected to the plurality of terminals by wirebonds. 
     
     
         10 . The microelectronic device of  claim 6 , wherein the one or more first dies comprise a plurality of dies comprising a NAND stack, and wherein the second die comprises a controller. 
     
     
         11 . The microelectronic device of  claim 6 , further comprising a spacer between at least two of the first dies. 
     
     
         12 . The microelectronic device of  claim 6 , wherein the second die is flush with the first side of the substrate. 
     
     
         13 . The microelectronic device of  claim 6  wherein a portion of the second die projects outside of the recess and beyond the substrate. 
     
     
         14 . The microelectronic device of  claim 6  wherein:
 the bond sites are first bond sites; 
 a portion of the second die projects outside of the recess and beyond the substrate; 
 the portion of the second die includes second bond sites; and 
 the microelectronic device further comprises wirebonds connecting the second terminals at the first side to the second bond sites. 
 
     
     
         15 . A microelectronic device, comprising:
 a substrate with first bond pads on a first side of the interposer substrate and second bond pads on a second side of the interposer substrate, wherein the substrate has a first thickness and is formed with a recess extending from the first side to an intermediate depth in the interposer substrate, and wherein the recess has a first planform area;   a die stack comprising a plurality of first dies in a stack, wherein a base die of the die stack is attached to the second side of the interposer substrate;   a second die having a second planform area that is substantially the same as the first planform area, the second die being attached in the recess;   an electrical pathway between the plurality of first dies and the second bond pads; and   wirebonds electrically connecting the second die to the first bond pads.   
     
     
         16 . The microelectronic device of  claim 15  wherein the electrical pathway between the dies and first bond pads comprises wirebonds. 
     
     
         17 . The microelectronic device of  claim 15 , further comprising spacers between the plurality of dies. 
     
     
         18 . The microelectronic device of  claim 15  wherein the die stack comprises at least one memory device. 
     
     
         19 . The microelectronic device of  claim 15 , wherein the second die is flush with the first side of the substrate. 
     
     
         20 . A microelectronic device, comprising:
 a substrate having a first side and a second side, the second side including a plurality of
 terminals, wherein— 
 the substrate includes a recess open at the first side and extending partially, but not completely, through the substrate, and 
 the recess includes a base and a recess sidewall; 
   one or more first dies attached to the second side of the substrate, the one or more first dies having integrated circuitry and bond sites electrically connected to the terminals; and   a first die in the recess and attached to the base of the recess, wherein—
 the first die includes a major surface and a die sidewall, 
 the major surface and the base have generally similar dimensions, and 
 the die sidewall and the recess sidewall have generally similar dimensions.