Semiconductor storage device

Abstract

A semiconductor storage device including a plurality of memory cells, each including a variable resistance element, and control circuitry that executes a first writing process of applying a first writing pulse to a memory cell to turn the memory cell state into a first resistance state and a second writing process of applying a second writing pulse of opposite polarity to the first writing pulse to turn the memory cell into a second resistance state, the memory cell from among the plurality of memory cells. The control circuitry, when the memory cell is placed in the second resistance state, after applying the first writing pulse to the memory cell, applies a reading pulse for a verify process of reading whether the variable resistance element is placed in the first resistance state or the second resistance state.

What is claimed is: 
     
         1 . A semiconductor storage device comprising:
 a plurality of memory cells, each comprising a variable resistance element; and   control circuitry that executes a first writing process of applying a first writing pulse to a memory cell to turn the memory cell state into a first resistance state and a second writing process of applying a second writing pulse of opposite polarity to the first writing pulse to turn the memory cell into a second resistance state, the memory cell from among the plurality of memory cells,   wherein the control circuitry, when the memory cell is placed in the second resistance state, after applying the first writing pulse to the memory cell, applies a reading pulse for a verify process of reading whether the variable resistance element is placed in the first resistance state or the second resistance state.   
     
     
         2 . The semiconductor storage device according to  claim 1 ,
 wherein, when the memory cell is not placed in the first resistance state as a result of the verify process, the control circuitry applies a reset pulse comprising the second writing pulse to the memory cell.   
     
     
         3 . The semiconductor storage device according to  claim 1 ,
 wherein, when the memory cell is not placed in the first resistance state as a result of the verify process, the control circuitry applies the first writing pulse with a pulse width made longer than the first writing pulse applied last, and executes the verify process, and   wherein the control circuitry applies a pulse that is weaker than the second writing pulse as the reset pulse.   
     
     
         4 . The semiconductor storage device according to  claim 1 ,
 wherein, when the memory cell is not placed in the first resistance state as a result of the verify process, the control circuitry applies a reset pulse comprising the second writing pulse to the memory cell, applies the first writing pulse with a pulse width made longer than the first writing pulse applied last, and executes the verify process in mentioned order,   wherein the control circuitry applies a pulse whose voltage amplitude is less than the second writing pulse as the reset pulse.   
     
     
         5 . The semiconductor storage device according to  claim 1 ,
 wherein the control circuitry, when applying the reset pulse, causes a current for writing to be less than when applying the second writing pulse.   
     
     
         6 . The semiconductor storage device according to  claim 1 ,
 wherein the control circuitry applies a pulse with a shorter pulse width than the second writing pulse as the reset pulse.   
     
     
         7 . The semiconductor storage device according to  claim 1 ,
 wherein, if the memory cell is not placed in the first resistance state as a result of the verify process, the control circuitry extends pulse width by adding a predetermined value to the pulse width of the first writing pulse applied last.   
     
     
         8 . The semiconductor storage device according to  claim 1 ,
 wherein, if the memory cell is not placed in the first resistance state as a result of the verify process, the control circuitry extends pulse width by multiplying the pulse width of the first writing pulse applied last by a predetermined value.   
     
     
         9 . The semiconductor storage device according to  claim 1 ,
 wherein, if the memory cell is not placed in the first resistance state as a result of the verify process, the control circuitry repeats applying a reset pulse comprising the second writing pulse to the memory cell, applying the same pulse as the first writing pulse applied last, and executing the verify process in mentioned order by a predetermined number of times.   
     
     
         10 . The semiconductor storage device according to  claim 1 ,
 wherein the first resistance state is a state in which the resistance value of the variable resistance element is equal to or more than a first criterion value and the second resistance state is a state in which the resistance value of the variable resistance element is less than a second criterion value.   
     
     
         11 . The semiconductor storage device according to  claim 1 ,
 wherein the first resistance state is a state in which the resistance value of the variable resistance element is less than a first criterion value and the second resistance state is a state in which the resistance value of the variable resistance element is equal to or more than a second criterion value.   
     
     
         12 . The semiconductor storage device according to  claim 10 ,
 wherein, if the memory cell is not placed in the first resistance state as a result of the verify process, the control circuitry applies a reset pulse comprising the second writing pulse to the memory cell, applies the first writing pulse more times than when it last applied the first writing pulse, and executes the verify process in mentioned order.   
     
     
         13 . The semiconductor storage device according to  claim 1 ,
 wherein, if the memory cell is not placed in the first resistance state even after having repeated the first writing pulse application and the verify process by a predetermined number of times, the control circuitry increases the amplitude of the voltage of the first writing pulse and initializes the pulse width of the first writing pulse and then repeats the first writing pulse application and the verify process.   
     
     
         14 . A controller comprising:
 a control circuitry configured to:
 execute a first writing process of applying a first writing pulse to a memory cell comprising a variable resistance element to turn the memory cell state into a first resistance state in which the resistance value of the variable resistance element meets a first criterion and a second writing process of applying a second writing pulse of opposite polarity to the first writing pulse to turn the memory cell into a second resistance state meeting a second criterion; 
 when the memory cell is placed in the second resistance state, after applying the first writing pulse to the memory cell, apply a reading pulse for a verify process of reading whether the variable resistance element is placed in the first resistance state or the second resistance state; and 
 when the memory cell is not placed in the first resistance state as a result of the verify process, the control circuitry applies a reset pulse comprising the second writing pulse to the memory cell, apply the first writing pulse with a pulse width made longer than the first writing pulse applied last, and executes the verify process in mentioned order. 
   
     
     
         15 . The controller according to  claim 14 ,
 wherein, when the memory cell is not placed in the first resistance state as a result of the verify process, the control circuitry extends pulse width by adding a predetermined value to the pulse width of the first writing pulse applied last.   
     
     
         16 . The controller according to  claim 14 ,
 wherein, when the memory cell is not placed in the first resistance state as a result of the verify process, the control circuitry extends pulse width by multiplying the pulse width of the first writing pulse applied last by a predetermined value.   
     
     
         17 . The controller according to  claim 14 ,
 wherein, when the memory cell is not placed in the first resistance state as a result of the verify process, the control circuitry repeats applying a reset pulse comprising the second writing pulse to the memory cell, applying the same pulse as the first writing pulse applied last, and executing the verify process in mentioned order by a predetermined number of times, and even after that, when the first writing is unsuccessful, the control circuitry applies the first writing pulse with a pulse width made longer than the first writing pulse applied last, followed by executing the verify process.   
     
     
         18 . A semiconductor storage device comprising:
 memory cells, each comprising a variable resistance element and a selection transistor; and   control circuitry that executes a first writing process of applying a first writing pulse to a memory cell to turn the memory cell state into a first resistance state in which the resistance value of the variable resistance element meets a first criterion and a second writing process of applying a second writing pulse of opposite polarity to the first writing pulse to turn the memory cell into a second resistance state meeting a second criterion   wherein the control circuitry, when the memory cell is placed in the second resistance state, after applying the first writing pulse to the memory cell, applies a reading pulse for a verify process of reading whether the variable resistance element is placed in the first resistance state or the second resistance state,   wherein, if the memory cell is not placed in the first resistance state as a result of the verify process, the control circuitry applies a reset pulse comprising the second writing pulse to the memory cell, applies the first writing pulse with a pulse width made longer than the first writing pulse applied last, and executes the verify process in mentioned order, and   wherein control circuitry reads a memory cell by detecting a current flowing through an appropriate bit line or word line and deciding whether a desired memory cell is placed in a high or low resistance state.   
     
     
         19 . The semiconductor storage device according to  claim 18 , wherein each of the memory cells are of a cross-point type ReRAM (Resistive Random Access Memory). 
     
     
         20 . The semiconductor storage device according to  claim 18 , wherein the variable resistance element is coupled to the word line and bit line without a switch in between,
 further comprising a nonlinear resistance element being coupled in series to the variable resistance element,   wherein the memory cells form a memory cell array of matrix type structure.