Performance-driven cache line memory access

Abstract

A system and technique for cache line memory access includes a processor, a sectored cache, a memory, a memory controller, and logic. The logic is executable to, responsive to a miss in the cache of a sector address requested by the processor, request a cache line from the memory. The cache line request is divided into first and second cache subline requests. A determination is made as to which of the first and second cache subline requests corresponds to the requested sector address. Responsive to determining that the first cache subline request corresponds to the requested sector address, the first cache subline request is placed into a high priority queue of the memory controller and the second cache subline request is placed into a low priority queue of the memory controller. Requests from the high priority queue are serviced before requests from the low priority queue.

Wat is claimed is: 
     
         1 . A system, comprising:
 a processor;   a sectored cache;   a memory;   a memory controller; and   logic executable to, responsive to a miss in the cache of a sector address requested by the processor:
 request a cache line from the memory; 
 divide the cache line request into a first cache subline request and a second cache subline request; 
 determine which of the first and second cache subline requests corresponds to the requested sector address; 
 responsive to determining that the first cache subline request corresponds to the requested sector address, place the first cache subline request into a high priority queue of the memory controller; 
 place the second cache subline request into a low priority queue of the memory controller; and 
 service requests from the high priority queue before servicing requests from the low priority queue. 
   
     
     
         2 . The system of  claim 1 , wherein the logic is executable to:
 responsive to placing the second cache subline request in the low priority queue, initiate a timer; and   responsive to expiration of the timer, service the second cache subline request.   
     
     
         3 . The system of  claim 1 , wherein the logic is executable to:
 determine bus utilization; and   responsive to the bus utilization being below a threshold, service the low priority queue.   
     
     
         4 . The system of  claim 1 , wherein the logic is executable to, responsive to receiving a sector address request corresponding to the second cache subline request, transfer the second cache subline request to the high priority queue. 
     
     
         5 . The system of  claim 1 , wherein the logic is executable to, responsive to receiving a castout request corresponding to a sector address of the second cache subline request, remove the second cache subline request from the low priority queue and write data corresponding to the address to the memory. 
     
     
         6 . The system of  claim 1 , wherein the logic is executable to structure the cache line request as a sector request vector and a sector priority vector. 
     
     
         7 . The system of  claim 6 , wherein values of the sector request vector indicate the sector addresses for the cache line request, and values of the sector priority vector indicate which of the sector addresses are requested by the processor. 
     
     
         8 . A computer program product for performance-driven cache line memory access, the computer program product comprising:
 a non-transitory computer readable medium having computer readable program code embodied therewith, the computer readable program code comprising computer readable program code configured to, responsive to a miss in a cache of a sector address requested by a processor:
 request a cache line from a memory; 
 divide the cache line request into a first cache subline request and a second cache subline request; 
 determine which of the first and second cache subline requests corresponds to the requested sector address; 
 responsive to determining that the first cache subline request corresponds to the requested sector address, place the first cache subline request into a high priority queue of a memory controller; 
 place the second cache subline request into a low priority queue of the memory controller; and 
 service requests from the high priority queue before servicing requests from the low priority queue. 
   
     
     
         9 . The computer program product of  claim 8 , wherein the computer readable program code is configured to:
 responsive to placing the second cache subline request in the low priority queue, initiate a timer; and   responsive to expiration of the timer, service the second cache subline request.   
     
     
         10 . The computer program product of  claim 8 , wherein the computer readable program code is configured to:
 determine bus utilization; and   responsive to the bus utilization being below a threshold, service the low priority queue.   
     
     
         11 . The computer program product of  claim 8 , wherein the computer readable program code is configured to, responsive to receiving a sector address request corresponding to the second cache subline request, transfer the second cache subline request to the high priority queue. 
     
     
         12 . The computer program product of  claim 8 , wherein the computer readable program code is configured to, responsive to receiving a castout request corresponding to a sector address of the second cache subline request, remove the second cache subline request from the low priority queue and write data corresponding to the address to the memory. 
     
     
         13 . The computer program product of  claim 8 , wherein the computer readable program code is configured to structure the cache line request as a sector request vector and a sector priority vector. 
     
     
         14 . The computer program product of  claim 8 , wherein the computer readable program code is configured to identify values of the sector request vector as indicating the sector addresses for the cache line request and identify values of the sector priority vector as indicating which of the sector addresses are requested by the processor. 
     
     
         15 . A system, comprising:
 a processor;   a sectored cache; and   logic executable to, responsive to a miss in the cache:
 generate a cache line request corresponding to the miss via a sector request vector and a sector priority vector, the sector request vector identifying sector addresses missing from the cache, and the sector priority vector identifying which sector address is requested by the processor and which sector address has not been requested from the processor. 
   
     
     
         16 . The system of  claim 15 , wherein the logic is executable to:
 place a request for the requested sector address into a high priority queue; and   place a request for the unrequested sector address into a low priority queue.   
     
     
         17 . The system of  claim 16 , wherein the logic is executable to service requests from the high priority queue before servicing requests from the low priority queue. 
     
     
         18 . The system of  claim 16 , wherein the logic is executable to:
 responsive to placing the request in the low priority queue, initiate a timer; and   responsive to expiration of the timer, service the request from the low priority queue.   
     
     
         19 . The system of  claim 16 , wherein the logic is executable to::
 determine bus utilization; and   responsive to the bus utilization being below a threshold, service the request from the low priority queue.   
     
     
         20 . The system of  claim 16 , wherein the logic is executable to, responsive to receiving from the processor the sector address from the low priority queue, transfer the respective request from the low priority queue to the high priority queue.