Radio-frequency devices with frequency-tuned body bias

Abstract

Radio-frequency (RF) devices are disclosed providing improved switching performance. An RF switch device includes one or more field-effect transistors (FETs) disposed between a first node and a second node. Each FET has a respective source, drain, gate, and body. A resonance circuit connects the body of each of the one or more FETs to a reference node. The resonance circuit may be configured to behave as an approximately closed circuit at low frequencies below a selected value. The resonance circuit may also be configured to behave as an approximately open circuit at an operating frequency. The approximately closed circuit allows removal of surface charge from the body to the reference node.

What is claimed is: 
     
         1 . A wireless device comprising:
 a transceiver configured to process radio-frequency signals;   an antenna in communication with the transceiver configured to facilitate transmission of an amplified radio-frequency signal;   a power amplifier connected to the transceiver and configured to generate the amplified radio-frequency signal; and   a switch connected to the antenna and the power amplifier and configured to selectively route the amplified RF signal to the antenna, the switch including at least one field-effect transistor (FET), the switch further including a resonance circuit that connects a respective body of each of the at least one field-effect transistor to a reference node, the resonance circuit configured to behave as an approximately closed circuit at low frequencies below a selected value and as an approximately open circuit at an operating frequency, the approximately closed circuit allowing removal of surface charge from the respective body to the reference node.   
     
     
         2 . The wireless device of  claim 1  wherein the field-effect transistor is a silicon-on-insulator (SOI) field-effect transistor. 
     
     
         3 . The wireless device of  claim 1  wherein the resonance circuit includes an LC circuit having an inductor electrically parallel with a capacitor. 
     
     
         4 . The wireless device of  claim 3  wherein the resonance circuit further includes a body switch configured to connect or disconnect the body to or from the reference node. 
     
     
         5 . The wireless device of  claim 4  wherein the body switch includes a second field-effect transistor. 
     
     
         6 . The wireless device of  claim 4  wherein the second field-effect transistor is configured to be OFF when the first field-effect transistor is ON to thereby float the body of the first field-effect transistor. 
     
     
         7 . The wireless device of  claim 5  wherein the second field-effect transistor is further configured to be ON when the first field-effect transistor is OFF to facilitate the removal of surface charge from the body to the reference node. 
     
     
         8 . The wireless device of  claim 1  wherein the reference node includes a ground node. 
     
     
         9 . The wireless device of  claim 1  further comprising a gate bias circuit connected to and configured to provide a bias signal to a gate of the field-effect transistor. 
     
     
         10 . The wireless device of  claim 1  wherein the first node is configured to receive an radio-frequency signal having a power value and the second node is configured to output the RF signal when the field-effect transistor is in an ON state. 
     
     
         11 . The wireless device of  claim 10  wherein the at least one field-effect transistor includes N field-effect transistors connected in series, the quantity N selected to allow the switch circuit to handle the power of the radio-frequency signal. 
     
     
         12 . A semiconductor die comprising:
 a semiconductor substrate;   at least one field-effect transistor (FET) formed on the semiconductor substrate; and   a resonance circuit that connects a respective body of each of the at least one FET to a reference node, the resonance circuit configured to behave as an approximately closed circuit at low frequencies below a selected value and as an approximately open circuit at an operating frequency, the approximately closed circuit allowing removal of surface charge from the respective body to the reference node.   
     
     
         13 . The semiconductor die of  claim 12  further comprising an insulator layer disposed between the FET and the semiconductor substrate. 
     
     
         14 . The semiconductor die of  claim 13  wherein the die is a silicon-on-insulator (SOI) die. 
     
     
         15 . The semiconductor die of  claim 12  wherein the resonance circuit includes an LC circuit having an inductor electrically parallel with a capacitor. 
     
     
         16 . The semiconductor die of  claim 15  wherein the resonance circuit further includes a body switch configured to connect or disconnect the body to or from the reference node. 
     
     
         17 . The semiconductor die of  claim 16  wherein the body switch includes a second field-effect transistor. 
     
     
         18 . The semiconductor die of  claim 17  wherein the second field-effect transistor is configured to be OFF when the first field-effect transistor is ON to thereby float the body of the first field-effect transistor and wherein the second field-effect transistor is further configured to be ON when the first field-effect transistor is OFF to facilitate the removal of surface charge from the body to the reference node. 
     
     
         19 . A method for fabricating a semiconductor die, the method comprising:
 providing a semiconductor substrate;   forming at least one field-effect transistor (FET) on the semiconductor substrate, each of the at least one FET having a respective gate and body;   forming a resonance circuit on the semiconductor substrate, the resonance circuit configured to behave as an approximately closed circuit at low frequencies below a selected value and as an approximately open circuit at an operating frequency; and   connecting the resonance circuit between the respective body of each of the at least one FET and a reference node to allow removal of surface charge from the respective body to the reference node when the resonance circuit is approximately closed.   
     
     
         20 . The method of  claim 19  further comprising forming an insulator layer between the FET and the semiconductor substrate.