Circuit-and-heat-dissipation assembly and method of making the same
Abstract
Disclosed herein is a circuit-and-heat-dissipation assembly which includes: a heat sink including a heat absorbing base and a heat dissipating element, the heat absorbing base having a circuit-forming surface and an element-forming surface, the heat dissipating element protruding from the element-forming surface for dissipating heat conducted from the heat absorbing base into an ambient environment; an insulator layer formed on the circuit-forming surface; and a patterned circuit formed on the insulator layer and having an electroless plating layer which has a patterned catalyst seed layer comprising an active metal and formed on the insulator layer, and a reduced metal layer formed on the catalyst seed layer. Also disclosed herein is a method of making the circuit-and-heat-dissipation assembly.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method of making a circuit-and-heat-dissipation assembly, comprising:
preparing a heat sink that includes a heat absorbing base and a heat dissipating element, the heat absorbing base having a circuit-forming surface and an element-forming surface, the heat dissipating element protruding from the element-forming surface for dissipating heat conducted from the heat absorbing base into an ambient environment; forming an insulator layer on the circuit-forming surface; and forming a patterned circuit on the insulator layer, wherein the patterned circuit is formed on the insulator layer by forming a patterned electroless plating layer on the insulator layer using electroless plating techniques, and wherein the patterned electroless plating layer is formed on the insulator layer by: forming a catalyst seed layer comprising an active metal on the insulator layer; and forming a reduced metal layer on the catalyst seed layer by reducing metal ions through the catalyst seed layer.
2 . The method as claimed in claim 1 , wherein the catalyst seed layer is a patterned catalyst seed layer.
3 . The method as claimed in claim 1 , wherein the catalyst seed layer is a non-patterned catalyst seed layer and is subjected to patterning.
4 . The method as claimed in claim 1 , wherein a patterned electroplating layer is formed on the electroless plating layer using electroplating techniques.
5 . The method as claimed in claim 2 , wherein the patterned catalyst seed layer is formed on the insulator layer by:
covering the insulator layer with a patterned mask, the patterned mask being formed with a pattern of through-holes that corresponds to a pattern of the patterned catalyst seed layer; and applying an ink containing the active metal onto the patterned mask to fill the through-holes with the ink.
6 . The method as claimed in claim 5 , wherein the pattern of the patterned mask is formed by laser ablation techniques.
7 . The method as claimed in claim 5 , wherein the circuit-forming surface of the heat absorbing base is curved in shape, the patterned mask being flexible and conforming to the circuit-forming surface when covering the insulator layer.
8 . The method as claimed in claim 1 , further comprising:
forming at least one hole in the insulator layer, such that the hole exposes a contact region of the circuit-forming surface and that the hole is aligned with a gap defined by two soldering ends of a pair of conductive lines of the patterned circuit; and forming a heat dissipating block on the contact region, such that the heat dissipating block extends from the contact region through the hole in the insulator layer and into the gap.
9 . The method as claimed in claim 1 , wherein the heat dissipating element is in the form of fins.
10 . The method as claimed in claim 1 , wherein the reduced metal layer is formed on the catalyst seed layer by reducing the metal ions in an electroless plating bath through the catalyst seed layer.Join the waitlist — get patent alerts
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