Multi-orientation integrated cell, in particular input/output cell of an integrated circuit

Abstract

An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a multiplexer coupled to a site of an integrated cell disposed at a location of an integrated circuit;   a first thin gate oxide transistor configured to exhibit normal operation in a first direction of orientation and degraded operation in a second direction of orientation, the first thin gate oxide transistor having a terminal coupled to a first input terminal of the multiplexer;   a second thin gate oxide transistor configured to exhibit normal operation in the second direction of orientation and degraded operation in the first direction of orientation, the second thin gate oxide transistor having a terminal coupled to a second input terminal of the multiplexer; and   a controller configured to detect a usability of the first thin gate oxide transistor and the second thin gate oxide transistor based on an electrical characteristic indicative of the first direction of orientation or the second direction of orientation, the controller being further configured to control the multiplexer to couple the terminal of the first thin gate oxide transistor or the terminal of the second thin gate oxide transistor to the site.   
     
     
         2 . The integrated circuit of  claim 1 , wherein an oxide thickness of at least one of the first thin gate oxide transistor or the second thin gate oxide transistor is less than or equal to about  2  nanometers. 
     
     
         3 . The integrated circuit of  claim 1 , wherein the controller comprises a detection circuit having two integrated test devices separate from the first thin gate oxide transistor and the second thin gate oxide transistor, a first one of the two integrated test devices being oriented in the first direction of orientation, a second one of the two integrated test devices being oriented in the second direction of orientation, the two integrated test devices being usable in each of the first direction of orientation and the second direction of orientation. 
     
     
         4 . The integrated circuit of  claim 3 , wherein each of the two integrated test devices comprises an element exhibiting the electrical characteristic according to first direction of orientation and the second direction of orientation and representative of the normal operation or the degraded operation of the first thin gate oxide transistor and the second thin gate oxide transistor. 
     
     
         5 . The integrated circuit of  claim 4 , wherein the controller further comprises a detector configured to analyze the electrical characteristic of the element of each of the two integrated test devices and to deliver a control signal to the multiplexer. 
     
     
         6 . The integrated circuit of  claim 4 , wherein the electrical characteristic comprises a threshold voltage of each of the two integrated test devices. 
     
     
         7 . The integrated circuit of  claim 3 , wherein each of the two integrated test devices comprises a thick gate oxide transistor, a longitudinal direction of each gate defining a direction of orientation of the thick gate oxide transistor. 
     
     
         8 . The integrated circuit of  claim 7 , wherein an oxide thickness of the thick gate oxide transistor is greater than or equal to about 3 nanometers. 
     
     
         9 . The integrated circuit of  claim 7 , wherein a gate length of the thick gate oxide transistor is greater than or equal to about 150 nanometers. 
     
     
         10 . A method of operating an integrated circuit, the method comprising:
 detecting, by a controller, a usability of a first integrated device and a second integrated device based on an electrical characteristic indicative of a first direction of orientation or a second direction of orientation, the first integrated device exhibiting normal operation in the first direction of orientation and degraded operation in the second direction of orientation, the second integrated device exhibiting degraded operation in the first direction of orientation and normal operation in the second direction of orientation;   sending, by the controller, a control signal to a multiplexer based on the usability of the first integrated device and the second integrated device detected by the controller; and   coupling, by the multiplexer and based on the control signal, a terminal of the first integrated device or a terminal of the second integrated device to a site of an integrated cell disposed at a location of an integrated circuit. ii. The method of  claim 10 , wherein the first direction of orientation is orthogonal to the second direction of orientation.   
     
     
         12 . The method of  claim 10 , wherein at least one of the first integrated device or the second integrated device comprises a thin gate oxide MOS transistor. 
     
     
         13 . The method of  claim 10 , wherein detecting, by the controller, the usability of the first integrated device and the second integrated device based on the electrical characteristic indicative of the first direction of orientation or the second direction of orientation comprises:
 detecting which one of two integrated test devices exhibits a higher electrical characteristic, a first one of the two integrated test devices being oriented in the first direction of orientation, a second one of the two integrated test devices being oriented in the second direction of orientation, the electrical characteristic being different in each of the first direction of orientation and the second direction of orientation.   
     
     
         14 . The method of  claim 13 , wherein the electrical characteristic comprises a threshold voltage. 
     
     
         15 . The method of  claim 13 , wherein the electrical characteristic comprises a leakage current. 
     
     
         16 . An integrated circuit, comprising:
 a first integrated device being operable in a first direction of orientation and exhibiting degraded operation in a second direction of orientation compared to the first direction of orientation;   a second integrated device being operable in the second direction of orientation and exhibiting degraded operation in the first direction of orientation compared to the second direction of orientation;   a multiplexer having input terminals coupled to the first integrated device and the second integrated device, the multiplexer being configured to couple, based on a control signal, the first integrated device or the second integrated device to a site of an integrated cell disposed at a location of the integrated circuit; and   a controller configured to determine an operability of the first integrated device and the second integrated device and generate the control signal based on the operability of the first integrated device and the second integrated device.   
     
     
         17 . The integrated circuit of  claim 16 , wherein the controller comprises:
 two integrated test devices, separate from the first integrated device and the second integrated device, respectively oriented in the first direction of orientation and the second direction of orientation, each integrated test device comprising an element exhibiting a characteristic according to a direction of orientation and representative of a usable or non-usable character of the first and second integrated devices; and   a comparator having a first input terminal coupled to a terminal of a first one of the two integrated test devices and a second input terminal coupled to a terminal of a second one of the two integrated test devices, the comparator configured to compare voltages at the first input terminal and the second input terminal and generate the control signal based on a comparison of the voltages.   
     
     
         18 . The integrated circuit of  claim 17 , wherein each of the two integrated test devices comprises a thick gate oxide transistor, a longitudinal direction of each gate defining a direction of orientation of the thick gate oxide transistor. 
     
     
         19 . The integrated circuit of  claim 16 , wherein the first direction of orientation is substantially perpendicular to the second direction of orientation. 
     
     
         20 . The integrated circuit of  claim 16 , wherein each of the first integrated device and the second integrated device comprises a thin gate oxide transistor having an oxide thickness less than or equal to about 2 nanometers.