Diode structures with controlled injection efficiency for fast switching

Abstract

This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

What is claimed is: 
     
         1 . A diode device disposed in a semiconductor substrate comprising:
 a heavily doped bottom layer of a first conductivity type supporting a lower buffer layer of the first conductivity type above the heavily doped bottom layer of a first conductivity type;   an upper buffer layer of the first conductivity type disposed below a top anode layer of a second conductivity type wherein the upper buffer layer is more heavily doped than the lower buffer layer to function as an ejection efficiency controlling buffer layer; and   a middle lightly doped buffer layer of the first conductivity type disposed between the upper buffer layer and the lower buffer layer of the first conductivity type.   
     
     
         2 . The diode device of  claim 1  wherein:
 the middle lightly doped buffer layer having a thickness larger than then the lower buffer layer of the first conductivity type. 
 
     
     
         3 . The diode device of  claim 1  further comprising:
 a trench gate opened from the top surface of the anode layer into a bottom of the upper heavily buffer layer filled with a gate conductive material and padded with a gate dielectic layer wherein the trench gate limiting an injection area of the top anode layer of a second conductivity type. 
 
     
     
         4 . The diode device of  claim 3  wherein:
 the trench gate is electrically connected to the top anode layer. 
 
     
     
         5 . The diode device of  claim 1  further comprising:
 a plurality of trench gates wherein each of the trench gates opened from the top surface of the anode layer into a bottom of the upper heavily buffer layer filled with a gate conductive material and padded with a gate dielectic layer and wherein the trench gates are configured as trench-gate pairs between trench gates having shorter distance and longer distance separating the trench-gate pairs; 
 each of the adjacent gate pairs surrounded and enclosing a region of the top anode layer and the upper buffer layer of the first conductivity type; and 
 a lightly doped region of the second conductivity type disposed below the top surface of the semiconductor substrate and above the middle lightly doped buffer layer of the first conductivity type between the trench-gate pairs. 
 
     
     
         6 . The diode device of  claim 5  wherein:
 the lightly doped region of the second conductivity type disposed between the trench-gate pairs is insulated by a dielectric layer from an anode electrode disposed on the top surface whereby the lightly doped region of the second conductivity type disposed between the trench-gate pairs is electrically floating. 
 
     
     
         7 . The diode device of  claim 1  further comprising:
 a plurality of trench gates wherein each of the trench gates opened from the top surface of the anode layer into a bottom of the upper heavily buffer layer filled with a gate conductive material and padded with a gate dielectic layer and wherein the trench gates are configured as trench-gate pairs between trench gates having shorter distance and longer distance separating the trench-gate pairs; 
 each of the adjacent gate pairs surrounded and enclosing a region of the top anode layer and the upper buffer layer of the first conductivity type; and 
 a plurality of lightly doped regions of the second conductivity type disposed below the top surface of the semiconductor substrate and surrounded by the middle lightly doped buffer layer of the first conductivity type extends between the trench-gate pairs. 
 
     
     
         8 . The diode device of  claim 5  wherein:
 the plurality of lightly doped regions of the second conductivity type disposed between the trench-gate pairs is insulated by an dielectric layer from an anode electrode disposed on the top surface whereby the lightly doped regions of the second conductivity type disposed between the trench-gate pairs is electrically floating. 
 
     
     
         9 . The diode device of  claim 1  further comprising:
 a plurality of trench gates wherein each of the trench gates opened from the top surface of the anode layer into a bottom of the upper heavily buffer layer filled with a gate conductive material and padded with a gate dielectic layer and wherein at least two adjacent trench gates surround and insulate a region of the top anode layer of the second conductivity type; 
 an anode electrode disposed on the top surface of the semiconductor substrate and is electrically connected to the trench gates and an external region of the top anode layer not insulated by the trench gates. 
 
     
     
         10 . The diode device of  claim 9  wherein:
 the adjacent trench gates surround the regions of the top anode layer of the second conductivity type as top insulate regions and the top insulated regions are covered by an dielectric layer to insulated from an anode electrode layer to form a plurality of floating body region of the second conductivity type. 
 
     
     
         11 . A diode device disposed in a semiconductor substrate comprising:
 a heavily doped bottom layer of a first conductivity type supporting a lower buffer layer of the first conductivity type above the heavily doped bottom layer of a first conductivity type;   an upper buffer layer of the first conductivity type disposed below a top anode layer of a second conductivity type wherein the upper buffer layer is more heavily doped than the first buffer layer to function as an ejection efficiency controlling buffer layer;   a middle lightly doped buffer layer of the first conductivity type disposed between the upper buffer layer and the lower buffer layer of the first conductivity type;   a plurality of trench gates wherein each of the trench gates opened from the top surface above the anode layer into a bottom of the upper heavily buffer layer filled with a gate conductive material and padded with a gate dielectic layer and wherein at least two adjacent trench gates surround and insulate a top region of the first conductivity type; and   an anode electrode disposed on the top surface of the semiconductor substrate and is in direct contact with the top anode layer and top region of the first conductivity type.   
     
     
         12 . The diode device of  claim 11  wherein:
 the heavily doped bottom layer of a first conductivity is formed as separated bottom layer segments surrounded by and below the lower buffer layer of the first conductivity type. 
 
     
     
         13 . The diode device of  claim 11  wherein:
 the separated bottom layer segments are disposed vertically below contact areas between the anode electrode and the top anode layer. 
 
     
     
         14 . The diode device of  claim 11  further comprising:
 a cathode electrode layer disposed below the heavily doped bottom layer. 
 
     
     
         15 . The diode device of  claim 1  further comprising:
 a cathode electrode layer disposed below the heavily doped bottom layer. 
 
     
     
         16 . A diode integrated with an integrated-gate bipolar transistor (IGBT) device in a semiconductor substrate comprising:
 a bottom layer comprises a first layer segment of heavily doped first conductivity type and a second segment of heavily doped second conductivity type wherein the bottom layer supporting a lower buffer layer of the first conductivity type disposed above the bottom layer;   an upper buffer layer of the first conductivity type disposed below a top anode layer of a second conductivity type wherein the upper buffer layer is more heavily doped than the first buffer layer to function as an ejection efficiency controlling buffer layer;   a middle lightly doped buffer layer of the first conductivity type disposed between the upper buffer layer and the lower buffer layer of the first conductivity type;   a plurality of trench gates wherein each of the trench gates opened from the top surface above the anode layer into a bottom of the upper heavily buffer layer filled with a gate conductive material and padded with a gate dielectic layer and wherein at least two adjacent trench gates surround and insulate a top region of the first conductivity type direct in contact with a top anode electrode layer; and   another two adjacent trench gates surround and insulate a region of the top anode layer as an IGBT body region encompassing an IGBT source region of the first conductivity therein and an IGBT planar gate disposed above the IGBT body region and the IGBT source region.   
     
     
         17 . The diode integrated with the IBGT device of  claim 16  wherein:
 the top anode electrode further contact a top surface of the IGBT source region and the IGBT body region to function as an emitter electrode for the IGBT. 
 
     
     
         18 . The diode integrated with the IBGT device of  claim 16  further comprising:
 an electrode layer disposed below the bottom layer to function as a cathode electrode for the diode and a collector electrode for the IGBT. 
 
     
     
         19 . The diode integrated with the IBGT device of  claim 16  wherein:
 the IGBT body region further encompasses an extension region of the upper buffer layer of the first conductivity type wherein the extension region of the first conductivity type extends vertically from the upper buffer layer to a top surface of the semiconductor substrate.