Semiconductor packages including interposer and methods of manufacturing the same

Abstract

A semiconductor package may include a semiconductor die mounted on a first surface of an interposer die so that a die connection portion of the semiconductor die faces to the first surface of the interposer die, a protection portion may be disposed on the first surface of the interposer die to cover the semiconductor die, and an interconnection structure disposed in and on the interposer die. The interconnection structure may include an external connection portion that is located on a second surface of the interposer die opposite to the semiconductor die, a through electrode portion that penetrates the interposer die to have an end portion combined with the die connection portion, and an extension portion that connects the through electrode portion to the external connection portion. Related methods are also provided.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor package, the method comprising:
 attaching a semiconductor die to a first surface of an interposer wafer so that die connection portions of the semiconductor die face towards the first surface;   forming a protecting portion covering the semiconductor die on the first surface of the interposer wafer;   reducing a thickness of the interposer wafer by recessing a second surface of the interposer wafer opposite to the semiconductor die;   forming via holes in the interposer wafer having the recessed second surface to expose the die connection portions; and   forming interconnection structures in the via holes and on the recessed second surface of the interposer wafer, each of the interconnection structures including a through electrode portion filling one of the via holes, an external connection portion disposed on the recessed second surface of the interposer wafer, and an extension portion connecting the through electrode portion to the external connection portion.   
     
     
         2 . The method of  claim 1 , wherein forming the interconnection structure comprises forming a conductive layer filling the via holes to provide the through electrode portions and extending onto the recessed second surface of the interposer wafer to provide the external connection portions and the extension portions. 
     
     
         3 . The method of  claim 2 , wherein the conductive layer is formed to directly contact the die connection portions exposed by the via holes. 
     
     
         4 . The method of  claim 1 , wherein the via holes are formed to be aligned with the die connection portions of the semiconductor die, respectively. 
     
     
         5 . The method of  claim 1 , wherein the external connection portions are formed to be offset from the die connection portions of the semiconductor die. 
     
     
         6 . The method of  claim 1 , wherein each of the external connection portions is formed to have a line width size which is greater than that of each of the through electrode portions. 
     
     
         7 . The method of  claim 1 , wherein the external connection portions are formed to have a pitch size which is greater than that of the through electrode portions. 
     
     
         8 . The method of  claim 1 , wherein the external connection portions are formed to have a line width size and pitch size different from a line width size and pitch size of the die connection portions. 
     
     
         9 . The method of  claim 1 , wherein the external connection portions are formed to have a line width size and pitch size larger than a line width size and pitch size of the end portions of the through electrode portions. 
     
     
         10 . The method of  claim 1 , wherein the semiconductor die is attached to the first surface of the interposer wafer using an adhesive layer. 
     
     
         11 . The method of  claim 1 , wherein recessing the second surface of the interposer wafer is performed so that the interposer wafer has a thickness of 5 nanometers to approximately 10 nanometers. 
     
     
         12 . The method of  claim 1 , further comprising attaching external connection terminals to the external connection portions. 
     
     
         13 . The method of  claim 12 , wherein the external connection terminal is spaced apart from the through electrode portion. 
     
     
         14 . The method of  claim 1 , wherein the external connection portion is spaced apart from the through electrode portion by a predetermined distance.