Quantum processor with instance programmable qubit connectivity

Abstract

In a quantum processor some couplers couple a given qubit to a nearest neighbor qubit (e.g., vertically and horizontally in an ordered 2D array), other couplers couple to next-nearest neighbor qubits (e.g., diagonally in the ordered 2D array). Couplers may include half-couplers, to selectively provide communicative coupling between a given qubit and other qubits, which may or may not be nearest or even next-nearest-neighbors. Tunable couplers selective mediate communicative coupling. A control system may impose a connectivity on a quantum processor, different than an “as designed” or “as manufactured” physical connectivity. Imposition may be via a digital processor processing a working or updated working graph, to map or embed a problem graph. A set of exclude qubits may be created from a comparison of hardware and working graphs. An annealing schedule may adjust a respective normalized inductance of one or more qubits, for instance to exclude certain qubits.

1 . A quantum processor comprising:
 a signal line;   a plurality of superconducting devices, wherein a respective device in the plurality of superconducting devices includes: a loop of superconducting metal interrupted by one or more Josephson junctions, and a first interface, in a first plurality of programming interfaces, for the plurality of superconducting devices, to control a normalized inductance of the respective device; and   a first plurality of tunable couplers between the signal line and first plurality of superconducting devices, each tunable coupler selective operable to mediate a communicable coupling between the signal line a respective one of the superconducting devices in the plurality of superconducting devices.   
     
     
         2 . The quantum processor of  claim 1  further comprising
 a second plurality of tunable couplers selectively operable to provide communicative coupling amongst the plurality of superconducting devices wherein a coupler of the plurality of couplers provides tunable communicative coupling between a respective pair of superconducting devices in the plurality of superconducting devices. 
 
     
     
         3 . The quantum processor of  claim 2  further comprising:
 a first device in the plurality of superconducting devices having a respective normalized inductance less than 1; 
 a second device in the plurality of superconducting devices having a respective normalized inductance less than 1; and 
 a first tunable coupler in the second plurality of tunable couplers that selectively provides a communicative coupling between the first device and the second device, wherein the first device, the second device, and the first tunable coupler are arranged in a first direction on the quantum processor. 
 
     
     
         4 . The quantum processor of  claim 3  further comprising:
 a third device in the plurality of superconducting devices having a respective normalized inductance less than 1; 
 a fourth device in the plurality of superconducting devices having a respective normalized inductance less than 1; 
 a second tunable coupler in the second plurality of tunable couplers that selectively provides a communicative coupling between the third device and the fourth device; and 
 wherein the third device, the fourth device, and the first tunable coupler are arranged in a second direction on the quantum processor, and one of the first device and the second device intersects the third device and the fourth device. 
 
     
     
         5 . The quantum processor of  claim 1  further comprising:
 a second set of programming interfaces operable to apply a dynamical annealing signal to each device in the plurality of superconducting devices via the signal line and a respective one of the tunable couplers of the first plurality of tunable couplers. 
 
     
     
         6 . The quantum processor of  claim 1  further comprising:
 a plurality of on-chip circuitry devices communicatively coupled to the first plurality of tunable couplers. 
 
     
     
         7 . The quantum processor of  claim 6  further comprising:
 a third set of programming interfaces operable to provide a plurality of preset digital values to the plurality of on-chip circuitry devices to convert the plurality of preset digital values to a plurality of analog signals to apply to the first plurality of tunable couplers. 
 
     
     
         8 . The quantum processor of  claim 1  wherein the first interface, in the first plurality of programming interfaces, for the plurality of superconducting devices, to control the respective normalized inductance of a respective device in the plurality of superconducting devices comprises a compound compound Josephson junction interrupting the loop of superconducting metal for the respective device in the plurality of superconducting devices. 
     
     
         9 . A quantum processing system, comprising:
 one or more signal lines;   at least one quantum processor that comprises:
 a plurality of superconducting devices, wherein a respective device in the plurality of superconducting devices includes a loop of superconducting metal interrupted by one or more Josephson junctions, and 
 a first plurality of tunable couplers between the one or more signal lines and first plurality of superconducting devices, each tunable coupler which selectively mediates a communicable coupling between the one or more signal lines a respective device in the first plurality of superconducting devices; and 
   at least one control system communicatively coupled to the at least one quantum processor to control a respective normalized inductance of each of at least some of the plurality of superconducting devices.   
     
     
         10 . The quantum processing system of  claim 9  wherein the at least one quantum processor further comprises:
 a second plurality of tunable couplers that selectively provide communicative coupling amongst the plurality of superconducting devices wherein a coupler of the second plurality of couplers provides tunable communicative coupling between a respective pair of superconducting devices in the plurality of superconducting devices. 
 
     
     
         11 . The quantum processing system of  claim 9  further comprising:
 a second set of programming interfaces operable to apply a dynamical annealing signal to each device in the plurality of superconducting devices via the at least one signal line and a respective tunable coupler of the first plurality of tunable couplers. 
 
     
     
         12 . The quantum processing system of  claim 9  further comprising:
 a plurality of on-chip circuitry devices communicatively coupled to the first plurality of tunable couplers. 
 
     
     
         13 . The quantum processing system of  claim 9  further comprising:
 a third set of programming interfaces operable to provide a plurality of preset digital values to the plurality of on-chip circuitry devices to convert the plurality of preset digital values to a plurality of analog signals to apply to the first plurality of tunable couplers. 
 
     
     
         14 . The quantum processing system of  claim 9  wherein:
 each respective device in the plurality of superconducting devices further comprises a compound compound Josephson junction that interrupts each respective loop of superconducting metal of the respective device in the plurality of superconducting devices. 
 
     
     
         15 . The quantum processing system of  claim 13  wherein:
 the at least one control system further comprises at least one signal line communicatively coupled a respective compound compound Josephson junction interrupting for the respective device in the plurality of superconducting devices.