Apparatus and Methods for Multi-Die Packaging

Abstract

A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate.

1 . A packaged semiconductor device comprising:
 a first package substrate having a first plurality of lead fingers;   a first die attached to a first major surface of the first package substrate;   a first plurality of interconnects coupled between the first plurality of lead fingers and the first die;   a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate;   a second die attached to a first major surface of the second package substrate, over the first die;   a second plurality of interconnects coupled between the second plurality of lead fingers and the second die; and   a single encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the single encapsulant: exposes a portion of the first package substrate and a portion of the second package substrate, is in direct contact with the first and second die, and fills a cavity between the first die and the second die.   
     
     
         2 . The packaged semiconductor device of  claim 1 , wherein the portion of the first package substrate is exposed at a first major surface of the packaged semiconductor device and the portion of the second package substrate comprises package contacts exposed at the first major surface of the packaged semiconductor device. 
     
     
         3 . The packaged semiconductor device of  claim 2 , wherein the single encapsulant exposes a second portion of the second package substrate at a second major surface of the packaged semiconductor device, opposite the first major surface of the packaged semiconductor device. 
     
     
         4 . The packaged semiconductor device of  claim 3 , wherein the second plurality of lead fingers are bent so as to extend from the first major surface to the second major surface of the packaged semiconductor device. 
     
     
         5 . The packaged semiconductor device of  claim 3 , wherein the first package substrate is at the first major surface of the packaged semiconductor device. 
     
     
         6 . The packaged semiconductor device of  claim 3 , further comprising a second packaged semiconductor device attached to the second exposed portion of the second package substrate. 
     
     
         7 . The packaged semiconductor device of  claim 1 , wherein the first plurality of interconnects and the second plurality of interconnects comprise wire bonds. 
     
     
         8 . The package semiconductor device of  claim 7 , wherein the wire bonds are completely surrounded by the single encapsulant. 
     
     
         9 . The packaged semiconductor device of  claim 1 , wherein the first major surface of the first package substrate faces the first major surface of the second package substrate such that the first die and the second die are between the first major surface of the first package substrate and the first major surface of the second package substrate and are completely surrounded by the single encapsulant. 
     
     
         10 . The packaged semiconductor device of  claim 1 , wherein the first package substrate comprises a lead frame. 
     
     
         11 . The packaged semiconductor device of  claim 10 , wherein the first plurality of lead fingers are separated from each other by a partial cut. 
     
     
         12 . The packaged semiconductor device of  claim 1 , where the first package substrate comprises a laminate substrate. 
     
     
         13 - 18 . (canceled) 
     
     
         19 . A packaged semiconductor device comprising:
 a first package substrate comprising a lead frame and a first plurality of lead fingers;   a first die attached to the first package substrate;   a first set of wire bonds coupled between the first plurality of lead fingers and the first die;   a second package substrate comprising a lead frame and having a second plurality of lead fingers, wherein each of the second plurality of lead fingers includes a package contact and extends over the first die, and the second package substrate is electrically isolated from the first package substrate;   a second die attached to the second package substrate, over the first die;   a second set of wire bonds coupled between the second plurality of lead fingers and the second die; and   an encapsulant surrounding and in direct contact with the first die, the first package substrate, the first set of wire bonds, the second die, the second set of wire bonds, and the second package substrate, wherein
 the encapsulant exposes a portion of the first package substrate and package contacts of the second package substrate at a first major surface of the packaged semiconductor device, and a portion of the second package substrate at a second major surface of the packaged semiconductor device, opposite the first major surface of the packaged semiconductor device, and 
 the second plurality of lead fingers are bent so as to extend from the first major surface to the second major surface of the packaged semiconductor device. 
   
     
     
         20 . The packaged semiconductor device of  claim 19 , wherein the first plurality of lead fingers are separated from each other by a partial cut. 
     
     
         21 . A packaged semiconductor device, comprising:
 a first die attached onto a first major surface of a first package substrate having a first plurality of lead fingers;   a second die attached onto a first major surface of second package substrate having a second plurality of lead fingers, wherein the second die is attached to a downset flag portion of the second package substrate and the second plurality of lead fingers extend from the flag portion to package contacts above the second die;   the second package substrate inverted over the first package substrate such that the second die is over the first die, the first major surface of the first package substrate faces the first major surface of the second package substrate, and the package contacts are coplanar with the first plurality of lead fingers; and   an encapsulating structure on the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulating structure exposes a portion of the first package substrate and the package contacts at a first major surface of the packaged semiconductor device.   
     
     
         22 . The packaged semiconductor device of  claim 21 , wherein forming the encapsulating structure exposes a portion of the second package substrate at a second major surface of the packaged semiconductor device opposite the first major surface. 
     
     
         23 . The packaged semiconductor device of  claim 21 , further comprising:
 the first and second die together are included in the packaged semiconductor device after the packaged semiconductor device has been singulated.   
     
     
         24 . The packaged semiconductor device of  claim 23 , wherein the first package substrate comprises a lead frame, and the first plurality of lead fingers are separated from each other. 
     
     
         25 . The packaged semiconductor device of  claim 21 , further comprising the second package substrate inverted over the first package substrate and the inverted second package substrate is placed on a carrier, wherein the package contacts of the inverted second package substrate are spaced apart from the first package substrate on the carrier. 
     
     
         26 . The packaged semiconductor device of  claim 21 , further comprising a second packaged semiconductor substrate attached to the exposed portion of the second package substrate.