Embedded die in panel method and structure

Abstract

Methods for an embedded die panel are disclosed and may include fabricating a first layered structure by: forming first redistribution layers on a first carrier, forming a first dielectric layer on the first redistribution layers and carrier, forming a mask pattern on the first dielectric layer exposing a portion of the first dielectric layer, forming a second dielectric layer on the exposed portion of the first dielectric layer, forming vias in the first and second dielectric layers, and forming second redistribution layers on the second dielectric layer. The mask pattern may be removed forming a die cavity defined by the second dielectric layer. A second layered structure coupled to the first layered structure may be formed comprising a second carrier, a third dielectric layer, third and fourth redistribution layers on opposite surfaces of the third dielectric layer, and a semiconductor die.

1 - 51 . (canceled) 
     
     
         52 . A semiconductor package comprising:
 a first layered structure, comprising a first pre-formed dielectric film and a first conductive layer;   a semiconductor die on a first surface of the first layered structure;   a second layered structure, comprising a second pre-formed dielectric film, on the semiconductor die and the first layered structure;   a third layered structure, comprising a third pre-formed dielectric film and a second conductive layer, on the second layered structure; and   electrical paths electrically coupling the first layered structure to the third layered structure.   
     
     
         53 . The semiconductor package of  claim 52 , wherein the second layered structure comprises the electrical paths. 
     
     
         54 . The semiconductor package of  claim 52 , comprising electrical interconnects on a second surface of the first layered structure, wherein the second surface is opposite the first surface. 
     
     
         55 . The semiconductor package of  claim 54 , wherein at least one of the electrical interconnects is electrically coupled to the first conductive layer. 
     
     
         56 . The semiconductor package of  claim 52 , wherein at least one of the electrical paths comprises pillars at a top conductive portion and a bottom conductive portion, and a solder cap electrically connecting the top conductive portion to the bottom conductive portion. 
     
     
         57 . The semiconductor package of  claim 52 , wherein at least one of the electrical paths comprises a copper pillar. 
     
     
         58 . The semiconductor package of  claim 52 , wherein at least one of the electrical paths comprises a through via. 
     
     
         59 . A semiconductor package, the semiconductor package comprising:
 a first layered structure comprising:
 a first pre-formed dielectric film; and 
 a first redistribution structure embedded in the first pre-formed dielectric film; 
   a semiconductor die on an upper surface of the first layered structure;   a second layered structure, comprising a second pre-formed dielectric film, on the semiconductor die and the first layered structure; and   a third layered structure comprising:
 a third pre-formed dielectric film; 
 a second redistribution structure in an upper area of the third layered structure; 
 a third redistribution structure in a bottom area of the third layered structure and embedded in the third pre-formed dielectric film; and 
 first electrical paths electrically coupling the second redistribution structure to the third redistribution structure, and 
   second electrical paths electrically coupling the first layered structure to the third layered structure.   
     
     
         60 . The semiconductor package of  claim 59 , wherein at least one of the second electrical paths comprises pillars at a top conductive portion and a bottom conductive portion, and a solder cap electrically connecting the top conductive portion to the bottom conductive portion. 
     
     
         61 . The semiconductor package of  claim 59 , wherein at least one of the second electrical paths comprises a copper pillar. 
     
     
         62 . The semiconductor package of  claim 59 , wherein at least one of the second electrical paths comprises a through via. 
     
     
         63 . The semiconductor package of  claim 59 , wherein one or both of the first layered structure and the third layered structure comprises a conductive trace on at least one respective surface. 
     
     
         64 . The semiconductor package of  claim 59 , comprising a fourth redistribution structure in a lower area of the first layered structure. 
     
     
         65 . The semiconductor package of  claim 64 , comprising third electrical paths electrically coupling the first redistribution structure to the fourth redistribution structure. 
     
     
         66 . The semiconductor package of  claim 59 , wherein the second layered structure comprises the second electrical paths. 
     
     
         67 . The semiconductor package of  claim 59 , comprising electrical interconnects on a bottom surface of the first layered structure. 
     
     
         68 . The semiconductor package of  claim 67 , wherein at least one of the electrical interconnects is electrically coupled to the first layered structure. 
     
     
         69 . A method for semiconductor packaging, the method comprising
 forming a first layered structure by:
 forming a first redistribution structure on a surface of a first carrier; and 
 attaching a first pre-formed dielectric film on the first redistribution structure such that the first redistribution structure is embedded in the first pre-formed dielectric film; 
   providing a semiconductor die on a first surface of the first layered structure;   attaching a second pre-formed dielectric film on the first layered structure and the semiconductor die;   forming a second layered structure comprising:
 embedding a second redistribution layer into a third pre-formed dielectric film; and 
   removing the first carrier;   wherein:
 electrical paths electrically couple the first layered structure to the second layered structure through the second pre-formed dielectric film; and 
 a surface of the second redistribution layer is exposed from the third pre-formed dielectric film and contacts the electrical paths. 
   
     
     
         70 . The method of  claim 69 , wherein the third pre-formed dielectric film contacts a top of the second pre-formed dielectric film. 
     
     
         71 . The method of  claim 69 , wherein at least one of the electrical paths is a through via.