Methods of Manufacturing Semiconductor Devices

Abstract

Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes an array having at least one first region and at least one second region. The first region includes at least one first device oriented in a first direction. The second region includes at least one second device oriented in a second direction. The second direction is different than the first direction.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 an array comprising a first region and a second region, the first region comprising the first device oriented in a first direction, the second region comprising the second device oriented in a second direction, the second direction being different than the first direction, wherein the first region and the second region comprise a cell, wherein the cell comprises one of the first region comprising devices oriented in a +y direction, another one of the first region comprising devices oriented in a −y direction, one of the second region comprising devices oriented in a +x direction, and another one of the second region comprising devices oriented in a −x direction.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the cell is repeated a plurality of times in the array. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the second direction is substantially perpendicular to the first direction. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the first device in the first region and the second device in the second region are coupled together in parallel. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the first device and the second device comprise a gate contact comprising a length, the gate contact being disposed over a junction between a first well and a second well over substantially the entire length of the gate contact. 
     
     
         6 . The semiconductor device according to  claim 5 , wherein the length of the gate contact of the first device in the first region extends in the first direction, and wherein the length of the gate contact of the second device in the second region extends in the second direction. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein the first device and the second device comprise high voltage field effect transistors (FET's) having a gate, the gate having a breakdown voltage, wherein the high voltage FETs are adapted to operate at a voltage higher than the breakdown voltage of the gate. 
     
     
         8 . The semiconductor device according to  claim 1 , wherein the array comprises a plurality of high voltage devices, wherein at least one of the plurality of high voltage devices is oriented in the y direction in the first region, and wherein at least one of the plurality of high voltage devices is oriented in the x direction in the second region. 
     
     
         9 . The semiconductor device according to  claim 8 , wherein each of the plurality of high voltage devices comprises a source contact, a gate contact, and a drain contact, the source contact being disposed over and adjacent to a first well disposed within the workpiece, the first well comprising a first type, the drain contact being disposed over and adjacent to a second well disposed within the workpiece adjacent the first well, the second well comprising a second type, a junction being disposed between the first well and the second well, and wherein each of the plurality of high voltage devices further comprises an isolation region disposed within the second well between the drain contact and the gate contact. 
     
     
         10 . The semiconductor device according to  claim 9 , wherein the workpiece comprises the second type and wherein each of the plurality of high voltage devices further comprises a third well disposed beneath the second well, the third well comprising the first type; or wherein the workpiece comprises the first type and wherein each of the plurality of high voltage devices further comprises a third well disposed beneath the first well, the third well comprising the second type. 
     
     
         11 . The semiconductor device according to  claim 10 , wherein each of the plurality of high voltage devices comprises a first gate contact proximate the source, the first gate contact being disposed over a portion of the first well, and wherein each of the plurality of high voltage devices comprises a second gate contact disposed between the first gate contact and the drain contact, the second gate contact being disposed over a portion of the first well, the junction, a portion of the second well, and a portion of the isolation region. 
     
     
         12 . The semiconductor device according to  claim 11 , wherein each of the plurality of high voltage devices comprises a single drain contact and two high voltage transistors coupled together in parallel, wherein each of the plurality of high voltage devices comprises two first gate contacts, two second gate contacts, and two source contacts, and wherein the single drain contact is shared by the two high voltage transistors. 
     
     
         13 . A semiconductor device comprising:
 an array comprising a first region and a second region, the first region comprising a first device oriented in a first direction, the second region comprising a second device oriented in a second direction, the second direction being different than the first direction, wherein the array comprises a plurality of the first region and a plurality of the second region arranged in rows, columns, or blocks, wherein a first block of the array comprises blocks of the first region oriented in the first direction, and wherein a second block of the array comprises blocks of the second region oriented in the second direction.   
     
     
         14 . A method of manufacturing a semiconductor device, the method comprising:
 forming a plurality of high voltage devices on a workpiece, wherein forming the plurality of high voltage devices comprises
 forming a plurality of isolation regions in the workpiece, 
 implanting a plurality of first wells in the workpiece, 
 implanting a plurality of second wells in the workpiece, 
 forming a junction between each adjacent first well and second well, 
 forming a drain contact over each of the plurality of second wells, 
 forming a source contact over each of the plurality of first wells, 
 forming a first gate over each of the plurality of first wells, and 
 forming a second gate over at least the junction, and 
   wherein forming the plurality of high voltage devices comprises forming the plurality of high voltage devices arranged in an array, the array comprising at least one first region and at least one second region, the first region comprising at least one first high voltage device oriented in a first direction, the second region comprising at least one second high voltage device oriented in a second direction, wherein the second direction is substantially perpendicular to the first direction, and
 wherein the first region and the second region comprise a cell, wherein the cell comprises one first region comprising devices oriented in a +y direction but not in an opposite −y direction, another first region comprising devices oriented in a −y direction but not in an opposite +y direction, one second region comprising devices oriented in a +x direction but not in an opposite −x direction, and another second region comprising devices oriented in a −x direction but not in an opposite +x direction, or 
 wherein the first region comprises high voltage devices oriented in both +/− directions along the first direction and in both +/− directions along the second direction, and wherein the at least second region comprises high voltage devices oriented in both +/− directions along the first direction and in both +/− directions along the second direction. 
   
     
     
         15 . The method according to  claim 14 , wherein the first region and the second region comprise a cell, wherein the cell comprises one first region comprising devices oriented in a +y direction but not in an opposite −y direction, another first region comprising devices oriented in a −y direction but not in an opposite +y direction, one second region comprising devices oriented in a +x direction but not in an opposite −x direction, and another second region comprising devices oriented in a −x direction but not in an opposite +x direction. 
     
     
         16 . The method according to  claim 14 , wherein the first region comprises high voltage devices oriented in both +/− directions along the first direction and in both +/− directions along the second direction, and wherein the at least second region comprises high voltage devices oriented in both +/− directions along the first direction and in both +/− directions along the second direction. 
     
     
         17 . A method of manufacturing a semiconductor device, the method comprising:
 forming an array on a workpiece, the array comprising at least one first region and at least one second region, the first region comprising at least one first device oriented in a first direction, the second region comprising at least one second device oriented in a second direction, the second direction being different than the first direction, wherein the first region and the second region comprise a cell, wherein the cell comprises one first region comprising devices oriented in a +y direction but not in an opposite −y direction, another first region comprising devices oriented in a −y direction but not in an opposite +y direction, one second region comprising devices oriented in a +x direction but not in an opposite −x direction, and another second region comprising devices oriented in a −x direction but not in an opposite +x direction.