Wafer Scale Monolithic CMOS-Integration of Free- and Non-Free-Standing Metal- and Metal Alloy-Based MEMS Structures in a Sealed Cavity

Abstract

An assembly of metallic MEMS structures directly fabricated on planarized CMOS substrates, containing the application-specific integrated circuit (ASIC), by direct deposition and subsequent microfabrication steps on the ASIC interconnect layers, with integrated capping for packaging, is provided. The MEMS structures comprise at least one MEMS device element, with or without moveable parts anchored on the CMOS ASIC wafer with electrical contact provided via the metallic interconnects of the ASIC. The MEMS structures can also be made of metallic alloys, conductive oxides and amorphous semiconductors. The integrated capping, which provides a sealed cavity, is accomplished through bonding pads defined in the post-processing of the CMOS substrate.

What is claimed is: 
     
         1 . A method, comprising:
 forming a CMOS ASIC with an ASIC interconnect layer including first metallic interconnects to receive MEMS device input signals, contact pads for ASIC processed output signals, and a cap bonding pad;   depositing a first mold layer on the ASIC interconnect layer;   forming a first lithographic pattern on the first mold layer;   etching the first lithographic pattern to form a first etched surface with MEMS anchor windows exposing the first metallic interconnects;   electroplating copper on the first etched surface to form a first electroplated copper surface;   planarizing the first electroplated copper surface to the first mold layer to render electroplated copper anchor structures in the MEMS anchor windows;   depositing a second mold layer on the first mold layer;   forming a second lithographic pattern on the second mold layer;   etching the second lithographic pattern to form a second etched surface with first MEMS feature windows;   electroplating copper on the second etched surface to form a second electroplated copper surface;   planarizing the second electroplated copper surface to the second mold layer;   etching the second mold layer to expose electroplated copper MEMS features;   forming a copper substrate;   forming a film on a first surface of the copper substrate;   forming a third lithographic pattern on the film;   etching the third lithographic pattern to expose a cap outline;   etching the copper substrate to form a cap with a cap recess within the cap outline; and   attaching the cap to the cap bonding pad such that the electroplated copper MEMS features reside within the cap recess.   
     
     
         2 . The method of  claim 1  wherein the cap is formed from a material selected from semiconductors, metals, metal alloys, metal oxides and dielectrics, including, Si, Cu, Ti, W, Al, Ag, Pt, Pd, Ru, HfB2, Indium Tin Oxide (ITO), SiO2, quartz, sapphire, or a combination of a thereof. 
     
     
         3 . The method of  claim 1  wherein the cap is defined through at least one of lithography, etching and grinding. 
     
     
         4 . The method of  claim 1  wherein the cap is further processed to form through-thickness holes to host through silicon vias (TSVs). 
     
     
         5 . The method of  claim 4  wherein the TSVs are in contact with the contact pads of the CMOS ASIC substrate after the final bonding. 
     
     
         6 . The method of  claim 1  further comprising forming an adhesion layer between the cap and the substrate. 
     
     
         7 . The method of  claim 1  wherein pressure in the cap recess is determined by the pressure at attaching the cap is performed. 
     
     
         8 . The method of  claim 1  wherein the electroplating is performed after depositing and patterning the second mold layer on the first mold layer to simultaneously form the MEMS anchor and main features. 
     
     
         9 . A method, comprising:
 forming a CMOS ASIC with an ASIC interconnect layer including first metallic interconnects to receive MEMS device input signals, contact pads for ASIC processed output signals, and a cap bonding pad;   depositing a first mold layer on the ASIC interconnect layer;   forming a first lithographic pattern on the first mold layer;   etching the first lithographic pattern to form a first etched surface with MEMS bottom electrode windows and MEMS top electrode anchor windows exposing the first metallic interconnects;   electroplating copper on the first etched surface to form a first electroplated copper surface;   planarizing the first electroplated copper surface to the first mold layer to render electroplated copper bottom electrode anchor structures and electroplated copper top electrode anchor structures in the MEMS bottom electrode windows and MEMS top electrode anchor windows;   depositing a second mold layer on the first mold layer;   forming a second lithographic pattern on the second mold layer;   etching the second lithographic pattern to form a second etched surface with first MEMS top electrode feature windows;   electroplating copper on the second etched surface to form a second electroplated copper surface;   planarizing the second electroplated copper surface to the second mold layer;   etching the second mold layer to expose electroplated copper MEMS top electrode features.   
     
     
         10 . The method of  claim 9  wherein the second electroplated copper surface includes MEMS anchor features and MEMS main features. 
     
     
         11 . The method of  claim 9  wherein the electroplated copper MEMS top electrode features include at least one hole to facilitate processing of features beneath a cap ceiling. 
     
     
         12 . The method of  claim 11  further comprising sealing the at least one hole to form a sealed cavity. 
     
     
         13 . The method of  claim 12  wherein sealing is performed using at least one of PVD, CVD electro deposition and electro-less deposition. 
     
     
         14 . The method of  claim 12  wherein sealing is performed using a material selected from semiconductors, metals, metal alloys, metal oxides and dielectrics, including, but not limited to Cu, Al, Ag, W, Pt, Pd, Ru, Co, Cd, Pb, Zn, Cadium Zinc Telluride (CZT), HfB2, In2O3, SnO2, Indium Tin Oxide (ITO) or a combination thereof. 
     
     
         15 . The method of  claim 12  wherein pressure in the sealed cavity is determined by the pressure at which sealing is performed.