Method to control d-ff circuit

Abstract

An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks.

What is claimed is: 
     
         1 . A method to control a D-FF circuit, comprising:
 choosing to output an input data signal or output a high impedance signal in accordance with supplying a first control clock to an input buffer;   choosing to output a data signal received from the input buffer or retain a currently output data signal in accordance with supplying a second control clock to a master flip-flop;   choosing to output a high-impedance signal or output a data signal received from the master flip-flop in accordance with supplying the second control clock to a master-slave switch;   choosing to retain a currently output data signal or output a data signal received from the master-slave switch in accordance with supplying the second control clock to a slave flip-flop;   outputting the second control clock in accordance with supplying an external clock to a first clock buffer; and   outputting the first control clock retards rising and/or falling edges of the second control clock in accordance with supplying the second control clock to a second clock buffer,   wherein the input buffer does not receive the second control clock, and   wherein none of the master flip-flop, the master-slave switch, and the slave flip-flop receive the first control clock.   
     
     
         2 . The method according to  claim 1 ,
 wherein the input buffer includes a clocked inverter, which operates in accordance with the first control clock, inputs an input data signal, and outputs the first data signal.   
     
     
         3 . The method to  claim 1 , further comprising:
 generating and outputting the first control clock based on the second control clock.   
     
     
         4 . The method according to  claim 1 ,
 wherein the first control clock comprises a first pair of complementary clocks, and   wherein the second control clock comprises a second pair of complementary clocks.