Power overlay structure and method of making same

Abstract

A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

What is claimed is: 
     
         1 . A semiconductor device package comprising:
 a first semiconductor device coupled to a first surface of a dielectric layer;   an interconnect layer coupled to a second surface of the dielectric layer, the interconnect layer extending through at least one opening in the dielectric layer to connect to at least one contact pad on a first surface of the first semiconductor device;   a first conductive contact layer disposed on a second surface of the first semiconductor device;   a first conductive shim coupled to the first semiconductor device by way of the first conductive contact layer; and   a first lead-frame joined to the first conductive shim.   
     
     
         2 . The semiconductor device package of  claim 1  wherein the first lead-frame is joined to the first conductive shim by one of a solder, braze, and weld joint. 
     
     
         3 . The semiconductor device package of  claim 1  wherein the first conductive shim and the first lead-frame are fabricated from a common copper slab. 
     
     
         4 . The semiconductor device package of  claim 1  further comprising:
 a second semiconductor device having a first surface coupled to the first surface of the dielectric layer; 
 a second conductive contact layer disposed on a second surface of the second semiconductor device; 
 a second conductive shim coupled to the second semiconductor device by way of the second conductive contact layer; and 
 a second lead-frame extending outward from the second conductive shim. 
 
     
     
         5 . The semiconductor device package of  claim 4  further comprising a thermal interface coupled to a top surface of the first conductive shim and a top surface of the second conductive shim. 
     
     
         6 . The semiconductor device package of  claim 4  wherein a top surface of the first conductive shim and a top surface of the second conductive shim are co-planar. 
     
     
         7 . The semiconductor device package of  claim 6  wherein the first semiconductor device and the second semiconductor device differ in height. 
     
     
         8 . The semiconductor device package of  claim 1  further comprising a thermal interface disposed on a top surface of the first conductive shim, the thermal interface comprising a thermally conductive and electrically insulating material. 
     
     
         9 . The semiconductor device package of  claim 8  further comprising a filler material disposed between the dielectric layer and the thermal interface and surrounding the first semiconductor device. 
     
     
         10 . A method for manufacturing a semiconductor device package comprising:
 coupling a first semiconductor device to a first side of a dielectric substrate;   forming at least one opening through a thickness of the dielectric substrate;   disposing an interconnect layer on a second side of the dielectric substrate and into the at least one opening to electrically couple the interconnect layer to at least one contact pad on a first surface of the first semiconductor device;   applying a first conductive contact layer on a second surface of the first semiconductor device; and   coupling a first conductive shim to the first semiconductor device by way of the first conductive contact layer, the first conductive shim having a lead-frame joined thereto.   
     
     
         11 . The method of  claim 10  further comprising coupling the first conductive shim to the first semiconductor device with a solder layer. 
     
     
         12 . The method of  claim 10  further comprising applying a filler material to surround the first semiconductor device, the first conductive contact layer, and at least a portion of the first conductive shim. 
     
     
         13 . The method of  claim 10  further comprising patterning the interconnect layer to define a plurality of metal interconnects. 
     
     
         14 . The method of  claim 10  further comprising:
 coupling a second semiconductor device to the first side of the dielectric substrate, the second semiconductor device thicker than the first semiconductor device; 
 electrically coupling at least one contact pad on a first surface of the second semiconductor device to the interconnect layer through at least another opening in the dielectric substrate; 
 applying a second conductive contact layer on a second surface of the second semiconductor device; and 
 coupling a second conductive shim to the second semiconductor device by way of the second conductive contact layer, the second conductive shim thinner than the first conductive shim. 
 
     
     
         15 . The method of  claim 14  further comprising applying a thermal interface atop the first and second conductive shims, the thermal interface comprising one of a thermal grease, a thermal adhesive, and a thermal paste. 
     
     
         16 . The method of  claim 14  further comprising sizing the first and second conductive shims such that the top surfaces thereof are co-planar when coupled to the first and second semiconductor devices. 
     
     
         17 . A semiconductor device package comprising:
 a plurality of semiconductor devices disposed on a dielectric substrate;   an interconnect layer extending through openings in the dielectric substrate to electrically couple with contact pads provided on respective first surfaces of the plurality of semiconductor devices;   a plurality of conductive shims positioned atop the plurality of semiconductor devices and electrically coupled to respective second surfaces thereof; and   at least one lead-frame joined to at least one of the plurality of conductive shims.   
     
     
         18 . The semiconductor device package of  claim 17  wherein the plurality of semiconductor devices are of differing thicknesses;
 wherein the plurality of conductive shims are of differing thicknesses; and 
 wherein respective top surfaces of the plurality of conductive shims are co-planar. 
 
     
     
         19 . The semiconductor device package of  claim 17  wherein the plurality of semiconductor devices comprises a first semiconductor device and a second semiconductor device, the second semiconductor device having a thickness greater than a thickness of the first semiconductor device; and
 wherein the plurality of conductive shims comprise a first conductive shim coupled to the first semiconductor device and a second conductive shim coupled to the second semiconductor device, the first conductive shim having a thickness greater than a thickness of the second conductive shim. 
 
     
     
         20 . The semiconductor device package of  claim 17  further comprising a layer of thermally conductive and electrically insulating material extending across top surfaces of the plurality of conductive shims. 
     
     
         21 . A semiconductor device package comprising:
 a dielectric layer;   at least one stacked assembly comprising:
 a semiconductor device having a first surface coupled to the dielectric layer; and 
 a conductive shim stacked atop the semiconductor device and coupled thereto with a conductive material; and 
   a metallization layer comprising at least one metal interconnect extending through at least one opening in the dielectric layer and forming a direct metallic connection with at least one contact pad on the first surface of the semiconductor device.   
     
     
         22 . The semiconductor device package of  claim 21  wherein the at least one stacked assembly comprises a plurality of stacked assemblies, each comprising a semiconductor device coupled to a conductive shim with a conductive material;
 wherein the top surfaces and the bottom surfaces of the plurality of stacked assemblies are co-planar; 
 wherein the semiconductor devices of the plurality of stacked assemblies are of varying heights; and 
 wherein the conductive shims of the plurality of stacked assemblies are of varying heights. 
 
     
     
         23 . The semiconductor device package of  claim 21  wherein the semiconductor device is coupled to the dielectric layer with an adhesive; and
 wherein the at least one metal interconnect extends through the dielectric layer and the adhesive. 
 
     
     
         24 . The semiconductor device package of  claim 21  further comprising a thermal interface applied to a top surface of the at least one stacked assembly, the thermal interface comprising a thermally conductive and electrically insulating material. 
     
     
         25 . The semiconductor device package of  claim 21  wherein the conductive material comprises solder. 
     
     
         26 . A method of manufacturing a semiconductor device package comprising:
 coupling at least one semiconductor device to a first surface of a dielectric layer with an adhesive;   metalizing a second surface of the dielectric layer and at least one via in the dielectric layer and the adhesive to form an interconnection layer electrically coupled to at least one contact pad on a first surface of the at least one semiconductor device;   positioning at least one conducting shim atop the at least one semiconductor device in a stacked arrangement; and   coupling the at least one conducting shim joined to the at least one semiconductor device with a conductive material.   
     
     
         27 . The method of  claim 26  further comprising curing the adhesive to secure the at least one semiconductor device to the dielectric layer. 
     
     
         28 . The method of  claim 26  further comprising forming the at least one via in the dielectric layer and the adhesive using one of a laser ablation, laser drilling, plasma etching, photo-definition, and mechanical drilling process. 
     
     
         29 . The method of  claim 26  wherein stacking the at least one conducting shim atop the at least one semiconductor device comprises stacking a first conducting shim atop a first semiconductor device and stacking a second conducting shim atop a second semiconductor device, the second semiconductor device differing in height from the first semiconductor device. 
     
     
         30 . The method of  claim 29  further comprising grinding at least one of a back surface of the first conducting shim and a back surface of the second conducting shim such that the back surfaces of the first and second conducting shims are co-planar. 
     
     
         31 . The method of  claim 26  further comprising applying a layer of electrically conductive and thermally insulating material on a back surface of the at least one conducting shim.