Semiconductor device

Abstract

In semiconductor devices with nonvolatile memory modules embedded therein, a technology is provided which facilitates evaluation of the nonvolatile memory characteristics. An MCU includes a CPU, a flash memory, and an FPCC that controls write or erase operations to the flash memory. The FPCC executes a program used to perform write or other operations to the flash memory, thereby performing write or other operations to the flash memory in accordance with a command issued by the CPU. In the MCU, the FCU is configured to execute test firmware to evaluate the flash memory. In addition, a RAM can be used by both the CPU and FCU.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a main processor that controls operation of the semiconductor device;   a rewritable nonvolatile memory; and   a memory controller that controls write and erase operations to the nonvolatile memory,   wherein the memory controller includes a storage unit that stores a control program used to perform read/write/erase operations to the nonvolatile memory and the memory controller reads the control program from the storage unit to perform read/write/erase operations to the nonvolatile memory in accordance with a command issued by the main processor, and   wherein the memory controller executes a test firmware to evaluate the nonvolatile memory.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the memory controller includes:
 a rewrite controller that controls write and erase operations to the nonvolatile memory; and   a general-purpose processor,   wherein, when the semiconductor device is in normal operation, the rewrite controller reads the control program from the storage unit and executes the control program for read/write/erase operations to the nonvolatile memory in accordance with a command issued by the main processor, and   wherein, when the semiconductor device is in test operation to evaluate the characteristics of the nonvolatile memory, the general-purpose processor executes the test firmware.   
     
     
         3 . The semiconductor device according to  claim 2 , comprising:
 an interface unit that functions as an interface between the main processor and the memory controller, receives a command issued by the main processor, and issues, to the memory controller, a command to meet specifications of the memory controller; and   a first selection unit that switches between the rewrite controller and the general-purpose processor to couple one of them to the interface unit,   wherein the first selection unit couples the rewrite controller to the interface unit when the semiconductor device is in normal operation, while coupling the general-purpose processor to the interface unit when the semiconductor device is in test operation.   
     
     
         4 . The semiconductor device according to  claim 3 , wherein the memory controller includes a volatile memory that stores the test firmware, and
 wherein, when the semiconductor device is in test operation, the general-purpose processor reads the test firmware from the volatile memory of the memory controller and executes the test firmware.   
     
     
         5 . The semiconductor device according to  claim 3 , comprising:
 a volatile memory that is shared by the main processor and the memory controller; and   a second selection unit that switches between the main processor and the memory controller to couple one of them to the volatile memory,   wherein the second selection unit couples the main processor to the volatile memory when the semiconductor device is in normal operation, while coupling the memory controller to the volatile memory when the semiconductor device is in test operation,   wherein the volatile memory stores the test firmware, and   wherein, when the semiconductor device is in test operation, the general-purpose processor reads the test firmware from the volatile memory and executes the test firmware.   
     
     
         6 . The semiconductor device according to  claim 1 , comprising:
 a volatile memory that is shared by the main processor and the memory controller; and   a selection unit that switches between the main processor and the memory controller to couple one of them to the volatile memory,   wherein the selection unit couples the main processor to the volatile memory when the semiconductor device is in normal operation, while coupling the memory controller to the volatile memory when the semiconductor device is in test operation,   wherein the memory controller includes:
 a rewrite controller that controls write and erase operations to the nonvolatile memory; and 
   wherein, when the semiconductor device is in normal operation, the rewrite controller reads the control program from the storage unit and executes the control program to perform read/write/erase operations to the nonvolatile memory in accordance with a command issued by the main processor, and   wherein, when the semiconductor device is in test operation to evaluate the characteristics of the nonvolatile memory, the rewrite controller reads the test firmware from the volatile memory and executes the test firmware.   
     
     
         7 . The semiconductor device according to  claim 1 ,
 wherein the storage unit included in the memory controller is a read-only memory.   
     
     
         8 . A semiconductor device, comprising:
 a main processor that controls an operation of the semiconductor device;   a rewritable nonvolatile memory;   a memory controller that controls write and erase operations to the nonvolatile memory;   a volatile memory that is shared by the main processor and the memory controller; and   a selection unit that switches between the main processor and the memory controller to couple one of them to the volatile memory,   wherein the memory controller includes a storage unit that stores a control program used to perform read/write/erase operations to the nonvolatile memory and the memory controller reads the control program from the storage unit to perform a read/write/erase operation to the nonvolatile memory in accordance with a command issued by the main processor.   
     
     
         9 . The semiconductor device according to  claim 8 ,
 wherein the selection unit couples the main processor to the volatile memory when the semiconductor device is in normal operation, while coupling the memory controller to the volatile memory when the semiconductor device is in test operation.   
     
     
         10 . A semiconductor device, comprising:
 a main processor that controls operation of the semiconductor device;   a rewritable nonvolatile memory;   a memory controller that controls write and erase operations to the nonvolatile memory;   a volatile memory that is shared by the main processor and the memory controller; and   a first selection unit that switches between the main processor and the memory controller to couple one of them to the volatile memory,   wherein the memory controller includes:
 a rewrite controller that controls write and erase operations to the nonvolatile memory; and 
 a general-purpose processor, 
   wherein the rewrite controller reads the control program from the storage unit and executes the control program to read/write/erase operations to the nonvolatile memory in accordance with a command issued by the main processor, and   wherein the semiconductor device includes:
 an interface unit that functions as an interface between the main processor and the memory controller, receives a command issued by the main processor, and issues, to the memory controller, a command to meet the specifications of the memory controller; and 
 a second selection unit that switches between the rewrite controller and the general-purpose processor to couple one of them to the interface unit. 
   
     
     
         11 . The semiconductor device according to  claim 10 ,
 wherein the second selection unit couples the rewrite controller to the interface unit when the semiconductor device is in normal operation, while coupling the general-purpose processor to the interface unit when the semiconductor device is in test operation, and   wherein the first selection unit couples the main processor to the volatile memory when the semiconductor device is in normal operation, while coupling the memory controller to the volatile memory when the semiconductor device is in test operation.   
     
     
         12 . A semiconductor device, comprising:
 a main processor that controls operation of the semiconductor device;   a memory macro that includes a rewritable nonvolatile memory and a memory controller used to perform read/write/erase operations to the nonvolatile memory;   a storage unit that is disposed outside the memory macro and stores test firmware used to evaluate the nonvolatile memory; and   a processor that is disposed outside the memory macro, is activated in accordance with a command issued by the main processor in test operation, and reads the test firmware stored in the storage unit to evaluate the nonvolatile memory.