Integrated circuit

Abstract

An Integrated circuit includes: a latch unit suitable for inverting a voltage level of a first node and driving a second node with the inverted voltage level of the first node, and inverting a voltage level of the second node and driving the first node with the inverted voltage level of the second node; and a sink unit coupled with one or more among the first and second nodes, and suitable for sinking a charge of the coupled node.

1 . (canceled) 
     
     
         2 . An integrated circuit, comprising:
 a latch unit suitable for inverting a voltage level of a first node and driving a second node with the inverted voltage level of the first node, and inverting a voltage level of the second node and driving the first node with the inverted voltage level of the second node; and   a sink unit coupled with one or more among the first and second nodes, and suitable for sinking a charge of the coupled node wherein the sink unit includes:   a first diode coupled in a direction toward a power source voltage between the power source voltage and one or more among the first and second nodes; and   a second diode coupled in the direction toward the power source voltage between a ground voltage and a node coupled with the first diode among the first and second nodes.   
     
     
         3 - 19 . (canceled) 
     
     
         20 . An integrated circuit, comprising:
 a first inversion driving block suitable for inverting a voltage level of a first node and driving a second node with the inverted voltage level of the first node, and sinking a charge of the second node; and   a second inversion driving block suitable for inverting a voltage level of the second node and driving the first node with the inverted voltage level of the second node, and sinking a charge of the first node.   
     
     
         21 . The integrated circuit of  claim 20 , wherein the first inversion driving block includes:
 an isolation layer defining a first active region formed over a substrate, and a second active region formed on one side of the first active region;   a first gate formed in the first active region, and coupled with the first node;   a first junction region formed over the substrate on both sides of the first gate;   a second gate formed in the second active region, and coupled with the first node;   a second junction region formed over the substrate on both sides of the second gate; and   a rectifier element formed in the second active region between the first junction region and the second junction region facing each other,   wherein a power source voltage is applied to the first junction region on the other side of the first gate,   wherein the second node is coupled with the first junction region on one side of the first gate and the second junction region on the other side of the second gate, and   wherein a ground voltage is applied to the second junction region on one side of the second gate.   
     
     
         22 . The integrated circuit of  claim 21 , further comprising:
 a well formed over the substrate corresponding to the first active region,   wherein the substrate and the well are complementarily conductive to each other.   
     
     
         23 . The integrated circuit of  claim 22 , further comprising:
 a first pick-up region formed in the well on one side of the isolation layer defining the first active region; and   a second pick-up region formed over the substrate on one side of the isolation layer defining the second active region.   
     
     
         24 . The integrated circuit of  claim 23 , further comprising an additional rectifier element formed of the first pick-up region, the well, the substrate, and the second pick-up region. 
     
     
         25 . The integrated circuit of  claim 24 , wherein the rectifier element includes an impurity region formed to be spaced apart from the second junction region, and complementarily conductive to the substrate. 
     
     
         26 . The integrated circuit of  claim 25 ,
 wherein a power source voltage is applied to the first pick-up region,   wherein a ground voltage is applied to the second pick-up region,   wherein a power source voltage is applied to the impurity region, and   wherein a reverse bias is applied to the rectifier element and the additional rectifier element.