Orthogonal frequency division multiplexing-code division multiple access system

Abstract

An orthogonal frequency division multiplexing (OFDM)-code division multiple access (CDMA) system is disclosed. The system includes a transmitter and a receiver. At the transmitter, a spreading and subcarrier mapping unit spreads an input data symbol with a complex quadratic sequence code to generate a plurality of chips and maps each chip to one of a plurality of subcarriers. An inverse discrete Fourier transform is performed on the chips mapped to the subcarriers and a cyclic prefix (CP) is inserted to an OFDM frame. A parallel-to-serial converter converts the time-domain data into a serial data stream for transmission. At the receiver, a serial-to-parallel converter converts received data into multiple received data streams and the CP is removed from the received data. A discrete Fourier transform is performed on the received data streams and equalization is performed. A despreader despreads an output of the equalizer to recover the transmitted data.

1 - 21 . (canceled) 
     
     
         22 . An apparatus for a user equipment (UE), comprising:
 a processor configured to:
 generate a polyphase sequence; and 
 determine an orthogonal sequence; 
   a spreading circuit configured to combine an input symbol with the polyphase sequence and to spread a combined result using the orthogonal sequence to obtain a plurality of symbols; and   a mapping circuit configured to map the plurality of symbols to a plurality of subcarriers.   
     
     
         23 . The apparatus of  claim 22 , further comprising:
 an inverse Fourier transform (IFT) circuit configured to perform IFT on the plurality of symbols mapped to the plurality of subcarriers to obtain time domain symbols.   
     
     
         24 . The apparatus of  claim 23 , wherein the IFT comprises at least one of an inverse fast Fourier transform (IFFT) and an inverse discrete Fourier transform (IDFT). 
     
     
         25 . The apparatus of  claim 23 , further comprising:
 a cyclic prefix (CP) insertion circuit configured to insert a CP into the time domain symbols.   
     
     
         26 . The apparatus of  claim 22 , wherein the processor is configured to:
 generate a generic polyphase sequence; and   shift the generic polyphase sequence, wherein the polyphase sequence is generated by shifting the generic polyphase sequence.   
     
     
         27 . The apparatus of  claim 26 , wherein the shift comprises a shift in phase of the generic polyphase sequence. 
     
     
         28 . The apparatus of  claim 26 , wherein the shift comprises a discrete Fourier transform (DFT) modulation of the generic polyphase sequence. 
     
     
         29 . The apparatus of  claim 26 , wherein different shifts of the generic polyphase sequence result in different polyphase sequences that are orthogonal to each other. 
     
     
         30 . The apparatus of  claim 22 , wherein the polyphase sequence is at least one of a quadratic phase sequence and a Zadoff-Chu sequence. 
     
     
         31 . The apparatus of  claim 22 , wherein the mapping circuit is configured to sequentially map the plurality of symbols to the plurality of subcarriers. 
     
     
         32 . A user equipment (UE), comprising:
 a spreading circuit configured to combine an input symbol with a polyphase sequence and to spread a combined result using an orthogonal sequence to obtain a plurality of symbols;   a mapping circuit configured to map the plurality of symbols to a plurality of subcarriers; and   an orthogonal frequency division multiplex (OFDM) transceiver, the OFDM transceiver comprising:
 an inverse Fourier transform (IFT) circuit configured to perform IFT on the plurality of symbols mapped to the plurality of subcarriers to obtain time domain symbols, wherein the IFT is at least one of an inverse fast Fourier transform (IFFT) and an inverse discrete Fourier transform (IDFT); and 
 a cyclic prefix (CP) insertion circuit configured to insert a CP into the time domain symbols. 
   
     
     
         33 . The UE of  claim 32 , wherein the UE further comprises a processor configured to:
 generate a generic polyphase sequence; and   shift the generic polyphase sequence; and   generate the polyphase sequence, wherein the polyphase sequence is derived by shifting the generic polyphase sequence.   
     
     
         34 . The UE of  claim 33 , wherein the processor is configured to shift the generic polyphase sequence by discrete Fourier transform (DFT) modulating the generic polyphase sequence. 
     
     
         35 . The UE of  claim 33 , wherein different shifts of the generic polyphase sequence result in different polyphase sequences that are orthogonal to each other. 
     
     
         36 . The UE of  claim 32 , wherein the polyphase sequence is a quadratic phase sequence, and wherein the quadratic phase sequence is a Zadoff-Chu sequence. 
     
     
         37 . The UE of  claim 32 , wherein the mapping circuit is configured to sequentially map the plurality of symbols to the plurality of subcarriers. 
     
     
         38 . A computer-readable medium having instructions stored thereon, the instructions, when executed by a computing device, cause the computing device to:
 generate a polyphase sequence based on a generic polyphase sequence;   combine an input symbol with the polyphase sequence and to spread a combined result using an orthogonal sequence to obtain a plurality of symbols; and   map the plurality of symbols to a plurality of subcarriers.   
     
     
         39 . The computer-readable medium of  claim 38 , wherein the polyphase sequence is generated by shifting the generic polyphase sequence. 
     
     
         40 . The computer-readable medium of  claim 38 , wherein the instructions, when executed by the computing device, further cause the computing device to:
 generate the orthogonal sequence, wherein the orthogonal sequence is selected from a set of orthogonal spreading codes.   
     
     
         41 . The computer-readable medium of  claim 38 , wherein the instructions to map the plurality of symbols to the plurality of subcarriers comprises instructions that when executed by the computing device, cause the computing device to:
 sequentially map the plurality of symbols to the plurality of subcarriers.