Non-volatile memory device including ferroelectrics and method of manufacturing the same

Abstract

A non-volatile memory device may include a semiconductor substrate, a ferroelectric layer, a source, a drain, a gate and a channel region. The semiconductor substrate may have a recess. The ferroelectric layer may be formed in the recess. The source may be arranged at a first side of the recess. The drain may be arranged at a second side of the recess opposite to the first side. The gate may be arranged on the ferroelectric layers. The channel region may be formed on the recess between the source and the drain.

1 . A non-volatile memory device comprising:
 a semiconductor substrate having a recess including a depth from an upper surface of the semiconductor substrate;   a single ferroelectric layer buried in the recess, wherein an upper surface the single ferroelectric layer and the upper surface of the semiconductor substrate are a same plane;   a source arranged at a first side of the single ferroelectric layer;   a drain arranged at a second side of the single ferroelectric layer, wherein the second side is located opposite to the first side with respect to the single ferroelectric layer; and   a gate arranged over the single ferroelectric layer,   wherein a channel region is formed in the semiconductor substrate along a contour of the recess and between the source and the drain.   
     
     
         2 . The non-volatile memory device of  claim 1 , wherein the source and the drain are located in first and second upper portions of the semiconductor substrate, respectively. 
     
     
         3 . The non-volatile memory device of  claim 1 , wherein the recess has a semi-spherical shape. 
     
     
         4 . The non-volatile memory device of  claim 1 , wherein the recess is formed in the semiconductor substrate with a vertical sidewall,
 wherein the vertical sidewall extends in a direction which is substantially perpendicular to an upper surface of the semiconductor substrate.   
     
     
         5 . The non-volatile memory device of  claim 1 , further comprising:
 a gate insulating layer interposed between the semiconductor substrate and the ferroelectric layer.   
     
     
         6 . The non-volatile memory device of claim I, wherein the ferroelectric layer comprises hafnium oxide. 
     
     
         7 . A non-volatile memory device comprising:
 a semiconductor substrate;   a storage member formed in the semiconductor substrate;   a source and a drain formed in the semiconductor substrate and at both sides of the storage member; and   a gate formed over the storage member,   wherein the storage member is formed of a ferroelectric material having varying polarization states depending on an electric field level which is applied from the gate to the storage member.   
     
     
         8 . (canceled) 
     
     
         9 . The non-volatile memory device of  claim 7 , wherein a channel region is formed along an interface between the semiconductor substrate and the storage member and between the source and the drain. 
     
     
         10 . The non-volatile memory device of  claim 7 , further comprising:
 a gate insulating layer interposed between the semiconductor substrate and the storage member.   
     
     
         11 . A method of manufacturing a non-volatile memory device, the method comprising:
 implanting impurities into a semiconductor substrate;   etching the semiconductor substrate to form a recess, wherein the recess defines a source and a drain in the semiconductor substrate;   forming a ferroelectric layer in the recess; and   forming a gate over the ferroelectric layer.   
     
     
         12 . The method of  claim 11 , wherein the etching of the semiconductor substrate to form the recess comprises:
 dry etching the semiconductor substrate.   
     
     
         13 . The method of  claim 11 , further comprising:
 forming a gate insulating layer in the recess and between the semiconductor substrate and the ferroelectric layer.   
     
     
         14 - 16 . (canceled)