Integrating vlsi-compatible fin structures with selective epitaxial growth and fabricating devices thereon

Abstract

Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom of first trenches formed between shallow trench isolation (STI) regions. The STI regions and first trench heights are at least 1.5 times their width. The STI regions are etched away to expose the top surface of the substrate to form second trenches between the first epitaxial regions. A layer of a spacer material is formed in the second trenches on sidewalls of the first epitaxial regions. Second epitaxial regions of a second type material are grown from the substrate surface at a bottom of the second trenches between the first epitaxial regions. Pairs of n- and p-type fins can be formed from the first and second epitaxial regions. The fins are co-integrated and have reduced defects from material interface lattice mismatch.

What is claimed is: 
     
         1 . An integrated circuit structure, comprising:
 a first semiconductor layer above a substrate, the first semiconductor layer having a top surface and walls;   a second semiconductor layer on the top surface of first semiconductor layer, the second semiconductor layer comprising a semiconductor material different than the first semiconductor layer, and the second semiconductor layer having a top surface and sidewalls, the sidewalls of the second semiconductor layer substantially vertically aligned with the sidewalls of the first semiconductor layer;   a semiconductor fin on the top surface of second semiconductor layer, the semiconductor fin comprising a semiconductor material different than the first semiconductor layer and different than the second semiconductor layer, wherein the semiconductor fin has a width narrower than a width of the second semiconductor layer; and   a dielectric spacer material conformal with the sidewalls of the second semiconductor layer and with the sidewalls of the first semiconductor layer, wherein a height of the dielectric spacer materials is greater than a width of the dielectric spacer material.   
     
     
         2 . The integrated circuit structure of  claim 1 , wherein the first semiconductor layer comprises Si70Ge30. 
     
     
         3 . The integrated circuit structure of  claim 2 , wherein the second semiconductor layer comprises Si30Ge70. 
     
     
         4 . The integrated circuit structure of  claim 3 , wherein the semiconductor fin comprises Ge. 
     
     
         5 . The integrated circuit structure of  claim 1 , wherein the first semiconductor layer comprises InP or GaAs. 
     
     
         6 . The integrated circuit structure of  claim 5 , wherein the second semiconductor layer comprises InAlAs. 
     
     
         7 . The integrated circuit structure of  claim 6 , wherein the semiconductor fin comprises InGaAs or InAs. 
     
     
         8 . The integrated circuit structure of  claim 1 , wherein the top surface of the first semiconductor layer in non-flat, and wherein the top surface of the second semiconductor layer is non-flat. 
     
     
         9 . The integrated circuit structure of  claim 1 , wherein the sidewalls of the first semiconductor layer are non-flat, and wherein the sidewalls of the second semiconductor layer are non-flat. 
     
     
         10 . The integrated circuit structure of  claim 9 , wherein the dielectric spacer material has substantially flat outermost sidewalls. 
     
     
         11 . An integrated circuit structure, comprising:
 a first semiconductor layer above a substrate, the first semiconductor layer having a top surface and sidewalls;   a second semiconductor layer on the top surface of first semiconductor layer, the second semiconductor layer comprising a semiconductor material different than the first semiconductor layer, and the second semiconductor layer having a top surface and sidewalls, the sidewalls of the second semiconductor layer substantially vertically aligned with the sidewalls of the first semiconductor layer;   a first semiconductor fin on the top surface of second semiconductor layer, the first semiconductor fin comprising a semiconductor material different than the first semiconductor layer and different than the second semiconductor layer;   a third semiconductor layer above the substrate and laterally adjacent to the first semiconductor layer, the third semiconductor layer having a top surface and sidewalls, the third semiconductor layer comprising a semiconductor material different than the semiconductor material of the first semiconductor fin, different than the second semiconductor layer and different than the first semiconductor layer;   a fourth semiconductor layer on the top surface of third semiconductor layer and laterally adjacent to the second semiconductor layer, the fourth semiconductor layer comprising a semiconductor material different than the third semiconductor layer, different than the semiconductor material of the first semiconductor fin, different than the second semiconductor layer and different than the first semiconductor layer, and the fourth semiconductor layer having a top surface and sidewalls, the sidewalls of the fourth semiconductor layer substantially vertically aligned with the sidewalls of the third semiconductor layer; and   a second semiconductor fin on the top surface of fourth semiconductor layer, the second semiconductor fin comprising a semiconductor material different than the fourth semiconductor layer, different than the third semiconductor layer, different than the semiconductor material of the first semiconductor fin, different than the second semiconductor layer and different than the first semiconductor.