Restructuring the computer and its association with the internet

Abstract

A computer operating system runs a computer. The computer operating system executes a computerized method including sending an RF signal to an external memory device, eliciting and receiving an input from the external memory device that identifies the external device and a set of files stored on the external memory device, and displaying the set of files on a display device of a computer. The external memory device can be any device with a memory, such as a thumb drive, camera, or the like.

1 . A computer system comprising:
 a microprocessor;   a random access memory (RAM) communicatively coupled to the microprocessor;   a first comparator associated with the random access memory that is loaded with a first random access memory location value;   a second comparator associated with the random access memory that is loaded with a second random access memory location value, the amount of memory between the first value and the second value being greater than an amount of memory needed to store an executable instruction set for an application; and   a fault triggered in response to when the application calls for memory locations outside the bounds of the memory between the first random access memory location value and the second random access memory location value.   
     
     
         2 . The computer system of  claim 1  wherein the computer system prevents further writing to the random access memory in response the fault being triggered. 
     
     
         3 . The computer system of  claim 1  further comprising an operating system that prevents writing of another executable code to the memory between the first random access memory location value and the second random access memory location. 
     
     
         4 . The computer system of  claim 1  further comprising an operating system that produces a prompt, in response to fault, seeking an input to add random access memory next to the random access memory between the first random access memory location and the second random access memory location. 
     
     
         5 . The computer system of  claim 1  wherein the fault indicates that the random access memory between the first random access memory location and the second random access memory location is full. 
     
     
         6 . The computer system of  claim 5  wherein the fault states that further operations require a restart of the computer system. 
     
     
         7 . The computer system of  claim 1  further comprising a third comparator associated with the random access memory that carries a third random access location value, an amount of random access memory being read between the random access memory location associated with the second comparator value and the random access memory location associated with the third comparator value. 
     
     
         8 . The storage system of  claim 1  further comprising:
 a fourth comparator associated with a fourth random access memory location value; and 
 a fifth comparator associated with a fifth random access memory location value, the amount of memory between the fourth random access memory value and the fifth random access memory value being greater than an amount of memory needed to operate a second executable instruction set. 
 
     
     
         9 . The computer system of  claim 8  wherein there is a space provided between the second random access memory location value and the fourth random access memory location value that is left unwritten. 
     
     
         10 . The computer system of  claim 9  wherein the space provided between the second random access memory location value and the fourth random access memory location is initially reserved for future expansion of either the ram memory for operations associated with the first executable instruction set or the ram memory for operations associated with the second executable instruction set. 
     
     
         11 . The computer system of  claim 9  wherein the space provided between the second random access memory location value and the fourth random access memory location is initially reserved for future expansion of either the ram memory for operations associated with the first executable instruction set or the ram memory for operations associated with the second executable instruction set. 
     
     
         12 . The computer system of  claim 8  wherein the second executable instruction set is the only instruction set allowed to use the linear contiguous ram between the fourth random access memory value and the fifth random access memory value. 
     
     
         13 . The computer system of  claim 8  wherein the second executable instruction set is the only instruction set allowed to use the ram between the fourth random access memory value and the fifth random access memory value, and wherein the first executable instruction set is the only instruction set allowed to use the ram between the first random access memory value and the second random access memory value. 
     
     
         14 . A computer system comprising:
 a microprocessor;   a random access memory communicatively coupled to the microprocessor;   a first comparator associated with the random access memory loaded with a first random access memory location value;   a second comparator associated with the random access memory loaded with a second random access memory location value, the amount of memory between the first value and the second value being greater than an amount of memory needed to store an executable instruction set for a single program; and   a latch which is triggered in response to an amount of executable instruction set is greater than the amount of memory between the first value of the comparator and the second value of the comparator, the latch, when triggered, produces a fault.   
     
     
         15 . The computer system of  claim 14  wherein the fault includes a message on a computer screen. 
     
     
         16 . A computer system comprising:
 a microprocessor;   a random access memory (RAM) communicatively coupled to the microprocessor;   a first comparator associated with the random access memory that is loaded with a first random access memory location value;   a second comparator associated with the random access memory that is loaded with a second random access memory location value, the amount of memory between the first value and the second value being greater than an amount of memory needed to store an executable instruction set for an application, the instruction set stored in non-transient memory, the instruction set being executable and causing the microprocessor to:   load a first memory location value and associate the first memory location value with a first memory location;   load a second memory location value and associate the second memory location value with a second memory location; and   trigger a fault in response to when the application calls for memory locations outside the bounds of the memory between the first random access memory location value and the second random access memory location value.   
     
     
         17 . The computer system of  claim 16  wherein the executable instruction set causes the microprocessor of the computer system to prevent further writing to the random access memory in response the triggering of the fault. 
     
     
         18 . The computer system of  claim 16  wherein the executable instruction set causes the microprocessor of the computer system to prevent writing of another executable code to the memory between the first random access memory location value and the second random access memory location. 
     
     
         19 . The computer system of  claim 16  wherein the executable instruction set causes the microprocessor of the computer system to produce a prompt, in response to the fault, the prompt seeking an input to add random access memory next to the random access memory between the first random access memory location and the second random access memory location. 
     
     
         20 . The computer system of  claim 16  wherein the executable instruction set causes the microprocessor of the computer system to require a restart of the computer system in response the triggering of the fault.