Semiconductor Device with Cell Trench Structures and Contacts and Method of Manufacturing a Semiconductor Device

Abstract

First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device, the method comprising:
 providing first and second cell trench structures extending from a first surface into a semiconductor portion, wherein the first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures;   providing a capping layer covering the first surface;   patterning the capping layer to form an opening having a minimum width larger than a thickness of the first insulator layer, the opening exposing a first vertical section of the first insulator layer at the first surface;   removing an exposed portion of the first insulator layer to form a recess between the semiconductor mesa and the first buried electrode; and   providing a contact structure in the recess and the opening,   
     
     
         2 . The method of  claim 1 , further comprising forming, in the semiconductor mesa, a source zone of a first conductivity type along the first surface and a body zone of a complementary second conductivity type at a first distance to the first surface, the first distance being smaller than a vertical extension of the recess. 
     
     
         3 . The method of  claim 2 , wherein the source zone is formed to extend from the first cell trench structure to the second cell trench structure and to separate the body zone from the first surface. 
     
     
         4 . The method of  claim 1 , wherein the opening is formed to expose, in addition to the first vertical sections of the first insulator layer, sections of the first buried electrode and the semiconductor mesa. 
     
     
         5 . The method of  claim 1 , wherein forming the recess comprises etching the first insulator layer selectively against the semiconductor mesa and the first buried electrode. 
     
     
         6 . The method of  claim 1 , wherein forming the opening in the capping layer and forming the recess between the semiconductor mesa the first buried electrode are combined in a single in-situ process. 
     
     
         7 . The method of  claim 1 , further comprising laterally widening the recess before providing the contact structure. 
     
     
         8 . The method of  claim 1 , forming the recess comprises laterally widening the recess in-situ. 
     
     
         9 . The method of  claim 1 , further comprising implanting, by a plasma implantation, impurities of the second conductivity type in a sidewall section of the semiconductor mesa exposed by the recess before providing the contact structure. 
     
     
         10 . The method of  claim 1 , further comprising implanting, by an ion beam implantation, impurities of the second conductivity type in a sidewall section of the semiconductor mesa exposed by the recess before providing the contact structure. 
     
     
         11 . A method of manufacturing a semiconductor device, the method comprising:
 introducing first and second cell trenches from a first surface into a semiconductor substrate, wherein first semiconductor mesas are formed between first and second cell trenches and second semiconductor mesas are formed between the first cell trenches;   providing a first insulator layer lining at least sidewalls of the first cell trenches;   providing first buried electrodes in the first cell trenches on the first insulator layer;   providing a capping layer covering the first surface;   patterning the capping layer to form first and second openings having a minimum width larger than a thickness of the first insulator layer, the first openings exposing first vertical sections of the first insulator layers adjoining the first semiconductor mesas, respectively, the second openings exposing the first buried electrodes of first cell trenches located between second semiconductor mesas;   removing exposed portions of the first insulator layers to form recesses between the first semiconductor mesas and the first buried electrodes; and   depositing a conductive material to form first contact structures in the recesses and the first openings and second contact structures in the second openings.   
     
     
         12 . The method of  claim 11 , further comprising widening the recesses before providing the first contact structures. 
     
     
         13 . The method of  claim 11 , further comprising implanting, by an ion beam implantation, impurities in sidewall sections of the first semiconductor mesas exposed by the recesses before providing the first contact structures. 
     
     
         14 . A semiconductor device comprising:
 first and second cell trench structures extending from a first surface into a semiconductor substrate, wherein first semiconductor mesas separate first and second cell trench structures and second semiconductor mesas separate the first cell trench structures, the first cell trench structures comprising a first buried electrode and a first insulator layer, respectively, and first vertical sections of the first insulator layers separate the first buried electrodes from the first semiconductor mesas;   a capping layer on the first surface;   first contact structures, each first contact structure comprising a first section in an opening of the capping layer and a second section between one of the first semiconductor mesas and one of the first buried electrodes directly adjoining the respective first semiconductor mesa.   
     
     
         15 . The semiconductor device of  claim 14 , wherein
 first sidewalls of the second sections of the first contact structures directly adjoin the first semiconductor mesas, and   second sidewalls directly adjoin the first buried electrodes and at least the second sidewalls are tilted to the first surface  101  by less than  90  degrees.   
     
     
         16 . The semiconductor device of  claim 15 , wherein the first and second sidewalls taper with increasing distance to the first surface and the second sidewalls deviate to a higher degree from a normal to the first surface than the first sidewalls of the second sections of the first contact structures. 
     
     
         17 . The semiconductor device of  claim 14 , further comprising second contact structures, each second contact structure formed in an opening of the capping layer and directly adjoining one of the first buried electrodes between two of the second semiconductor mesas. 
     
     
         18 . The semiconductor device of  claim 14 , wherein the first insulator layer has a uniform width. 
     
     
         19 . The semiconductor device of  claim 14 , wherein a width of the first insulator layer is equal to or less than a width of the second sections of the first contact structures. 
     
     
         20 . The semiconductor device of  claim 14 , wherein the second sections of the first contact structures are located in a vertical projection of first vertical sections of the first insulator layers.