Circuits and Methods For Impedance Calibration

Abstract

A driver circuit drives data to an output based on an input data signal in a transmission mode. The driver circuit includes transistors. A comparator generates a comparison output in a calibration mode based on a reference signal and a signal at the output of the driver circuit. A calibration control circuit adjusts an equivalent resistance of the transistors in the driver circuit based on the comparison output in the calibration mode. The equivalent resistance of the transistors in the driver circuit can be adjusted to support the transmission of data according to multiple different data transmission protocols using transmission links having different characteristic impedances. The equivalent resistance of the transistors in the driver circuit can also be adjusted to compensate for resistance in the package routing conductors and/or to compensate for parasitic resistance.

What is claimed is: 
     
         1 . An impedance calibration circuit comprising:
 a driver circuit that generates data at an output based on an input data signal in a transmission mode, wherein the driver circuit comprises first transistors;   a comparator that generates a comparison output in a calibration mode based on a reference signal and a signal at the output of the driver circuit; and   a calibration control circuit that adjusts an equivalent resistance of the first transistors based on the comparison output in the calibration mode to generate a first final calibrated code for the first transistors,   wherein the calibration control circuit adjusts the first final calibrated code to provide a first offset to the first final calibrated code based on first control signals that indicate the first offset, and   wherein the impedance calibration circuit uses the first final calibrated code to set the equivalent resistance of the first transistors during the transmission mode.   
     
     
         2 . The impedance calibration circuit of  claim 1 , wherein the first offset provided to the first final calibrated code by the calibration control circuit is a digital offset. 
     
     
         3 . The impedance calibration circuit of  claim 1 , wherein the first offset provided to the first final calibrated code by the calibration control circuit is an analog offset. 
     
     
         4 . The impedance calibration circuit of  claim 1 , wherein the calibration control circuit adjusts the reference signal based at least in part on the first offset indicated by the first control signals. 
     
     
         5 . The impedance calibration circuit of  claim 1 , wherein the calibration control circuit receives the first control signals that indicate the first offset, and wherein the first control signals are separate signals from the first final calibrated code. 
     
     
         6 . The impedance calibration circuit of  claim 1 , wherein the driver circuit further comprises second transistors, wherein the calibration control circuit adjusts an equivalent resistance of the second transistors based on the comparison output in the calibration mode to generate a second final calibrated code for the second transistors,
 wherein the calibration control circuit adjusts the second final calibrated code to provide a second offset to the second final calibrated code based on second control signals that indicate the second offset, and   wherein the impedance calibration circuit uses the second final calibrated code to set the equivalent resistance of the second transistors during the transmission mode.   
     
     
         7 . The impedance calibration circuit of  claim 6 , wherein the driver circuit further comprises a third transistor coupled to the second transistors, and a fourth transistor coupled to the third transistor and the first transistors, and wherein the third and fourth transistors drive the data to the output based on the input data signal in the transmission mode. 
     
     
         8 . The impedance calibration circuit of  claim 6 , wherein the calibration control circuit receives the second control signals that indicate the second offset, and wherein the second control signals are separate signals from the second final calibrated code. 
     
     
         9 . The impedance calibration circuit of  claim 1 , wherein the calibration control circuit shifts bits of the first final calibrated code left or right based on the first offset. 
     
     
         10 . An impedance calibration circuit comprising:
 a driver circuit that generates data at an output based on an input data signal in a transmission mode, wherein the driver circuit comprises first transistors;   a comparator that generates a comparison output based on a first reference signal and a signal at the output of the driver circuit during a first part of a calibration mode;   a reference voltage generator circuit that generates the first reference signal based on first control signals; and   a calibration control circuit that adjusts an equivalent resistance of the first transistors based on the comparison output during the first part of the calibration mode,   wherein the calibration control circuit adjusts the first control signals that set the first reference signal based on a first offset indicated by second control signals.   
     
     
         11 . The impedance calibration circuit of  claim 10 , wherein the reference voltage generator circuit generates a second reference signal based on the first control signals, wherein the calibration control circuit adjusts the first control signals based on a second offset indicated by third control signals, and wherein the comparator generates the comparison output based on the second reference signal and the signal at the output of the driver circuit during a second part of the calibration mode. 
     
     
         12 . The impedance calibration circuit of  claim 11 , wherein the driver circuit further comprises second transistors, and wherein the calibration control circuit adjusts an equivalent resistance of the second transistors based on the comparison output during the second part of the calibration mode. 
     
     
         13 . The impedance calibration circuit of  claim 10 , wherein the reference voltage generator circuit comprises a first current source circuit that generates a first tracking current to track temperature and process variations, a second current source circuit that generates a second tracking current to track temperature and process variations, and a pass gate circuit coupled to the first and the second current source circuits. 
     
     
         14 . The impedance calibration circuit of  claim 10 , wherein the first offset indicated by the second control signals is an analog offset. 
     
     
         15 . A method for calibrating an impedance of a driver circuit, the method comprising:
 generating data at an output of the driver circuit based on an input data signal during a transmission mode;   generating a comparison output using a comparator circuit during a calibration mode based on a comparison between a reference signal and a signal at the output of the driver circuit;   adjusting an equivalent resistance of first transistors in the driver circuit based on the comparison output during the calibration mode using a calibration control circuit to generate a first final calibrated code for the first transistors;   adjusting the first final calibrated code using the calibration control circuit to provide a first offset to the first final calibrated code based on first control signals that indicate the first offset; and   setting the equivalent resistance of the first transistors during the transmission mode using the first final calibrated code having the first offset.   
     
     
         16 . The method of  claim 15  further comprising:
 adjusting the reference signal based at least in part on the first offset indicated by the first control signals using the calibration control circuit. 
 
     
     
         17 . The method of  claim 15  further comprising:
 adjusting an equivalent resistance of second transistors in the driver circuit based on the comparison output during the calibration mode using the calibration control circuit to generate a second final calibrated code for the second transistors; 
 adjusting the second final calibrated code using the calibration control circuit to provide a second offset to the second final calibrated code based on second control signals that indicate the second offset; and 
 setting the equivalent resistance of the second transistors during the transmission mode using the second final calibrated code having the second offset. 
 
     
     
         18 . The method of  claim 17 , wherein generating data at the output of the driver circuit based on the input data signal during the transmission mode comprises driving the data to the output of the driver circuit based on the input data signal in the transmission mode using third and fourth transistors,
 wherein the third transistor is coupled to the second transistors, and the fourth transistor is coupled to the third transistor and the first transistors.   
     
     
         19 . The method of  claim 15  further comprising:
 receiving the first control signals that indicate the first offset at the calibration control circuit, wherein the first control signals and the first final calibrated code are separate sets of signals. 
 
     
     
         20 . The method of  claim 15 , wherein adjusting the first final calibrated code using the calibration control circuit to provide the first offset to the first final calibrated code based on the first control signals comprises shifting bits of the first final calibrated code left or right based on the first offset.