US2017237363A1PendingUtilityA1

Power control circuit

Assignee: RENESAS ELECTRONICS CORPPriority: Sep 19, 2014Filed: May 3, 2017Published: Aug 17, 2017
Est. expirySep 19, 2034(~8.1 yrs left)· nominal 20-yr term from priority
G01R 19/0092H02M 7/5387H03K 17/687H02M 1/084H02M 2001/0009H02M 1/0009
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Claims

Abstract

A power control circuit according to one embodiment includes an H-bridge circuit formed using a plurality of power transistors. The power transistors are respectively connected to current measurement circuits that measure currents flowing through the power transistors. Each of the power transistors includes a main emitter and a sense emitter through which a current corresponding to a current flowing through the main emitter flows. Each of the current measurement circuits measures a current flowing through each of the power transistors by using a current flowing through the sense emitter included in the power transistor. A control circuit controls the power transistors based on current values respectively measured by the current measurement circuits.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A power control circuit comprising:
 first and second power transistors respectively forming a top arm and a bottom arm of a first phase;   third and fourth power transistors respectively forming a top arm and a bottom arm of a second phase;   first to fourth diodes respectively in inverse-parallel connection with the first to fourth power transistors;   first to fourth current measurement circuits that respectively measure currents flowing through the first to fourth power transistors;   first to fourth gate drive circuits that output drive voltages for respectively driving the first to fourth power transistors;   a control circuit that controls the first to fourth gate drive circuits based on current values respectively measured by the first to fourth current measurement circuits; and   a load circuit having a first terminal connected to an output node of the first phase and a second terminal connected to an output node of the second phase, wherein   each of the first to fourth power transistors includes a main emitter or main source, and a sense emitter or sense source through which a current corresponding to a current flowing through the main emitter or main source flows,   the first to fourth current measurement circuits respectively measure currents flowing through the first to fourth power transistors by using currents flowing through the sense emitter or sense source included in the first to fourth power transistors, and   the control circuit obtains a current value flowing through the load circuit by using output values from the first to fourth current measurement circuits;   wherein the main emitter or source of each of the first to fourth power transistors coupled to a first low-voltage power supply, the sense emitter or source of each of the first to fourth power transistors coupled to a second low-voltage power supply, and the voltage of the second low-voltage power supply is lower than the voltage of the first low-voltage power supply.   
     
     
         2 . The power control circuit according to  claim 1 , wherein
 the voltage of the first low-voltage power supply is a ground potential and the voltage of the second low-voltage power supply is a negative potential.   
     
     
         3 . The power control circuit according to  claim 1 , wherein
 each of the first to fourth current measurement circuits comprises:
 an operational amplifier having a first input terminal connected to the sense emitter or sense source and a second input terminal connected to the main emitter or main source, 
 a resistor element having one end connected to the sense emitter or sense source and another end connected to a first node, and 
 an adjustment transistor placed between the first node and the second low-voltage power supply and having a base or gate supplied with an output of the operational amplifier, wherein 
   the operational amplifier adjusts a current flowing through the adjustment transistor so that a voltage of the main emitter or main source and a voltage of the sense emitter or sense source are substantially the same.   
     
     
         4 . The power control circuit according to  claim 1 , wherein the control circuit determines a maximum value of output values from the first to fourth current measurement circuits as a current value flowing through the load circuit. 
     
     
         5 . The power control circuit according to  claim 1 , wherein
 when currents are detected by the first current measurement circuit and the fourth current measurement circuit, the control circuit determines that a current flows from the first terminal to the second terminal of the load circuit, and   when currents are detected by the second current measurement circuit and the third current measurement circuit, the control circuit determines that a current flows from the second terminal to the first terminal of the load circuit.   
     
     
         6 . The power control circuit according to  claim 3 , wherein the adjustment transistor is placed outside a semiconductor chip forming the current measurement circuit. 
     
     
         7 . The power control circuit according to  claim 1 , wherein the control circuit controls at least one of a pulse width, a duty ratio and a pulse density of drive voltages to be supplied to the first to fourth power transistors in accordance with current values respectively measured by the first to fourth current measurement circuits. 
     
     
         8 . The power control circuit according to  claim 7 , wherein
 when a maximum value of current values respectively measured by the first to fourth current measurement circuits is smaller than a current command value, the control circuit extends a period where the first and third power transistors are ON and/or reduces a period where the second and fourth power transistors are ON, and   when a maximum value of current values respectively measured by the first to fourth current measurement circuits is larger than the current command value, the control circuit reduces a period where the first and third power transistors are ON and/or extends a period where the second and fourth power transistors are ON.   
     
     
         9 . The power control circuit according to  claim 1 , wherein, when a current is not detected in all of the first to fourth current measurement circuits, the control circuit estimates a current value flowing through the load circuit by using an inductance of the load circuit, a voltage applied to the load circuit, and past current values measured by the first to fourth current measurement circuits.

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