Method for conrolling on time of power switch in power converter

Abstract

A method for controlling a power switch of a power converter includes: detecting whether a zero current event occurs; generating an error signal; generating an adjusted voltage by multiplying a setting voltage by a ratio of an on time during which of the power switch is turned on in a previous switching cycle to a time length of the previous switching cycle; performing a low-pass filtering operation on the adjusted voltage to generate a filtered signal; providing a transconductance amplifier for converting the filtered signal into a ramp signal; turning on the power switch when the zero current event occurs; and turning off the power switch and rapidly lowering the level of the ramp signal when the ramp signal is greater than or equal to the error signal.

What is claimed is: 
     
         1 . A method for controlling a power switch ( 113 ) of a flyback power converter ( 100 ), the flyback power converter ( 100 ) comprising a primary side coil ( 107 ), a secondary side coil ( 109 ), and an inductive coil ( 111 ), wherein the primary side coil ( 107 ) is coupled between an input voltage signal (Vin) and the power switch ( 113 ), the secondary side coil ( 109 ) is configured to operably provide an output voltage signal (Vout) and an output current signal (lout), the inductive coil ( 111 ) is configured to operably sense the primary side coil ( 107 ) to generate an inductive signal (SS), and the power switch ( 113 ) is coupled between the primary side coil ( 107 ) and a fixed-voltage terminal, the method comprising:
 detecting the inductive signal (SS) to determine whether a zero current event occurs;   generating an error signal (COMP) corresponding to the output voltage signal (Vout) or the output current signal (Iout) according to a reference signal (Vref);   generating an adjusted voltage (Vset 2 ) less than a setting voltage (Vset) by multiplying the setting voltage (Vset) by a ratio of an on time during which of the power switch ( 113 ) is turned on in a previous switching cycle to a time length of the previous switching cycle;   performing a low-pass filtering operation on the adjusted voltage (Vset 2 ) to generate a filtered signal (VF);   providing a transconductance amplifier ( 350 ) configured to operably convert the filtered signal (VF) into a ramp signal (RAMP);   providing a capacitor ( 360 ) configured to be coupled with an output terminal of the transconductance amplifier ( 350 );   comparing the ramp signal (RAMP) with the error signal (COMP);   turning on the power switch ( 113 ) when the zero current event occurs; and   when the ramp signal (RAMP) is greater than or equal to the error signal (COMP), turning off the power switch ( 113 ) and rapidly lowering the level of the ramp signal (RAMP).   
     
     
         2 . The method of  claim 1 , wherein an on time (Ton) during which the power switch ( 113 ) is turned on in each switching cycle is directly proportional to a capacitance value of the capacitor ( 360 ) and a voltage value of the error signal (COMP), but is inversely proportional to a voltage value of the adjusted voltage (Vset 2 ) and a transconductance value of the transconductance amplifier ( 350 ). 
     
     
         3 . The method of  claim 2 , wherein the on time (Ton) during which the power switch ( 113 ) is turned on in each switching cycle is determined by the following formula:
     T on=( C ramp* V comp)/[ V set2* Gm]     wherein Ton denotes the on time at which the power switch ( 113 ) is turned on in each switching cycle, Cramp denotes a capacitance value of the capacitor ( 360 ), Vcomp denotes a voltage value of the error signal (COMP), Vset 2  denotes a voltage value of the adjusted voltage (Vset 2 ), and Gm denotes a transconductance value of the transconductance amplifier ( 350 ).   
     
     
         4 . The method of  claim 2 , wherein the ratio of the on time during which of the power switch ( 113 ) is turned on in the previous switching cycle to the time length of the previous switching cycle is directly proportional to a duty ratio of a control signal (CTL) utilized for controlling the power switch ( 113 ). 
     
     
         5 . The method of  claim 2 , wherein the operation of generating the adjusted voltage (Vset 2 ) comprises:
 providing a first switch ( 310 ) configured to be coupled between a setting signal input terminal ( 302 ) and a node ( 304 ), wherein the setting signal input terminal ( 302 ) is utilized for receiving the setting voltage (Vset);   providing a second switch ( 320 ) configured to be coupled between the node ( 304 ) and a fixed-voltage terminal; and   switching the first switch ( 310 ) and the second switch ( 320 ) alternatively to render the node ( 304 ) to provide the adjusted voltage (Vset 2 ).   
     
     
         6 . The method of  claim 2 , wherein the operation of rapidly lowering the level of the ramp signal (RAMP) comprises:
 providing a third switch ( 370 ) configured to be coupled between the output terminal of the transconductance amplifier ( 350 ) and a fixed-voltage terminal; and   turning on the third switch ( 370 ) when the ramp signal (RAMP) is greater than or equal to the error signal (COMP).   
     
     
         7 . A method for controlling a power switch ( 113 ) of an asynchronous-type buck-boost power converter ( 400 ), the asynchronous-type buck-boost power converter ( 400 ) comprising a first coil ( 407 ), an inductive coil ( 411 ), and a diode ( 415 ), wherein the first coil ( 407 ) is coupled between an input voltage signal (Vin) and the power switch ( 113 ), the inductive coil ( 411 ) is configured to operably sense the first coil ( 407 ) to provide an inductive signal (SS), the power switch ( 113 ) is coupled between the first coil ( 407 ) and a fixed-voltage terminal, and the diode ( 415 ) is coupled between the first coil ( 407 ) and a load ( 119 ) of the asynchronous-type buck-boost power converter ( 400 ), the method comprising:
 detecting the inductive signal (SS) to determine whether a zero current event occurs;   generating an error signal (COMP) corresponding to an output voltage signal (Vout) or an output current signal (lout) of the asynchronous-type buck-boost power converter ( 400 ) according to a reference signal (Vref);   generating an adjusted voltage (Vset 2 ) less than a setting voltage (Vset) by multiplying the setting voltage (Vset) by a ratio of an on time during which of the power switch ( 113 ) is turned on in a previous switching cycle to a time length of the previous switching cycle;   performing a low-pass filtering operation on the adjusted voltage (Vset 2 ) to generate a filtered signal (VF);   providing a transconductance amplifier ( 350 ) configured to operably convert the filtered signal (VF) into a ramp signal (RAMP);   providing a capacitor ( 360 ) configured to be coupled with an output terminal of the transconductance amplifier ( 350 );   comparing the ramp signal (RAMP) with the error signal (COMP);   turning on the power switch ( 113 ) when the zero current event occurs; and   when the ramp signal (RAMP) is greater than or equal to the error signal (COMP), turning off the power switch ( 113 ) and rapidly lowering the level of the ramp signal (RAMP).   
     
     
         8 . The method of  claim 7 , wherein an on time (Ton) during which the power switch ( 113 ) is turned on in each switching cycle is directly proportional to a capacitance value of the capacitor ( 360 ) and a voltage value of the error signal (COMP), but is inversely proportional to a voltage value of the adjusted voltage (Vset 2 ) and a transconductance value of the transconductance amplifier ( 350 ). 
     
     
         9 . The method of  claim 8 , wherein the on time (Ton) during which the power switch ( 113 ) is turned on in each switching cycle is determined by the following formula:
     T on=( C ramp* V comp)/[ V set2* Gm]     wherein Ton denotes the on time at which the power switch ( 113 ) is turned on in each switching cycle, Cramp denotes a capacitance value of the capacitor ( 360 ), Vcomp denotes a voltage value of the error signal (COMP), Vset 2  denotes a voltage value of the adjusted voltage (Vset 2 ), and Gm denotes a transconductance value of the transconductance amplifier ( 350 ).   
     
     
         10 . The method of  claim 8 , wherein the ratio of the on time during which of the power switch ( 113 ) is turned on in the previous switching cycle to the time length of the previous switching cycle is directly proportional to a duty ratio of a control signal (CTL) utilized for controlling the power switch ( 113 ). 
     
     
         11 . The method of  claim 8 , wherein the operation of generating the adjusted voltage (Vset 2 ) comprises:
 providing a first switch ( 310 ) configured to be coupled between a setting signal input terminal ( 302 ) and a node ( 304 ), wherein the setting signal input terminal ( 302 ) is utilized for receiving the setting voltage (Vset);   providing a second switch ( 320 ) configured to be coupled between the node ( 304 ) and a fixed-voltage terminal; and   switching the first switch ( 310 ) and the second switch ( 320 ) alternatively to render the node ( 304 ) to provide the adjusted voltage (Vset 2 ).   
     
     
         12 . The method of  claim 8 , wherein the operation of rapidly lowering the level of the ramp signal (RAMP) comprises:
 providing a third switch ( 370 ) configured to be coupled between the output terminal of the transconductance amplifier ( 350 ) and a fixed-voltage terminal; and   turning on the third switch ( 370 ) when the ramp signal (RAMP) is greater than or equal to the error signal (COMP).   
     
     
         13 . A method for controlling a power switch ( 113 ) of a synchronous-type buck-boost power converter ( 500 ), the synchronous-type buck-boost power converter ( 500 ) comprising a first coil ( 407 ), an inductive coil ( 411 ), and a second power switch ( 515 ), wherein the first coil ( 407 ) is coupled between an input voltage signal (Vin) and the power switch ( 113 ), the inductive coil ( 411 ) is configured to operably sense the first coil ( 407 ) to provide an inductive signal (SS), the first power switch ( 113 ) is coupled between a second terminal of the first coil ( 407 ) and a fixed-voltage terminal, and the second power switch ( 515 ) is coupled between the second terminal of the first coil ( 407 ) and a load ( 119 ) of the synchronous-type buck-boost power converter ( 500 ), the method comprising:
 detecting the inductive signal (SS) to determine whether a zero current event occurs;   generating an error signal (COMP) corresponding to an output voltage signal (Vout) or an output current signal (lout) of the synchronous-type buck-boost power converter ( 500 ) according to a reference signal (Vref);   generating an adjusted voltage (Vset 2 ) less than a setting voltage (Vset) by multiplying the setting voltage (Vset) by a ratio of an on time during which of the power switch ( 113 ) is turned on in a previous switching cycle to a time length of the previous switching cycle;   performing a low-pass filtering operation on the adjusted voltage (Vset 2 ) to generate a filtered signal (VF);   providing a transconductance amplifier ( 350 ) configured to operably convert the filtered signal (VF) into a ramp signal (RAMP);   providing a capacitor ( 360 ) configured to be coupled with an output terminal of the transconductance amplifier ( 350 );   comparing the ramp signal (RAMP) with the error signal (COMP);   turning on the power switch ( 113 ) when the zero current event occurs; and   when the ramp signal (RAMP) is greater than or equal to the error signal (COMP), turning off the power switch ( 113 ) and rapidly lowering the level of the ramp signal (RAMP).   
     
     
         14 . The method of  claim 13 , wherein an on time (Ton) during which the power switch ( 113 ) is turned on in each switching cycle is directly proportional to a capacitance value of the capacitor ( 360 ) and a voltage value of the error signal (COMP), but is inversely proportional to a voltage value of the adjusted voltage (Vset 2 ) and a transconductance value of the transconductance amplifier ( 350 ). 
     
     
         15 . The method of  claim 14 , wherein an on time (Ton) during which the power switch ( 113 ) is turned on in each switching cycle is determined by the following formula:
     T on=( C ramp* V comp)/[ V set2* Gm]     wherein Ton denotes the on time at which the power switch ( 113 ) is turned on in each switching cycle, Cramp denotes a capacitance value of the capacitor ( 360 ), Vcomp denotes a voltage value of the error signal (COMP), Vset 2  denotes a voltage value of the adjusted voltage (Vset 2 ), and Gm denotes a transconductance value of the transconductance amplifier ( 350 ).   
     
     
         16 . The method of  claim 14 , wherein the ratio of the on time during which of the power switch ( 113 ) is turned on in the previous switching cycle to the time length of the previous switching cycle is directly proportional to a duty ratio of a control signal (CTL) utilized for controlling the power switch ( 113 ). 
     
     
         17 . The method of  claim 14 , wherein the operation of generating the adjusted voltage (Vset 2 ) comprises:
 providing a first switch ( 310 ) configured to be coupled between a setting signal input terminal ( 302 ) and a node ( 304 ), wherein the setting signal input terminal ( 302 ) is utilized for receiving the setting voltage (Vset);   providing a second switch ( 320 ) configured to be coupled between the node ( 304 ) and a fixed-voltage terminal; and   switching the first switch ( 310 ) and the second switch ( 320 ) alternatively to render the node ( 304 ) to provide the adjusted voltage (Vset 2 ).   
     
     
         18 . The method of  claim 14 , wherein the operation of rapidly lowering the level of the ramp signal (RAMP) comprises:
 providing a third switch ( 370 ) configured to be coupled between the output terminal of the transconductance amplifier ( 350 ) and a fixed-voltage terminal; and   turning on the third switch ( 370 ) when the ramp signal (RAMP) is greater than or equal to the error signal (COMP).